top.vhd

MODELSIM开发的模拟CPU

    	clk, reset:	in  STD_LOGIC;
    	m_en, m_rw: out STD_LOGIC;    	
	aBus:	out STD_LOGIC_VECTOR(adrLength-1 downto 0);
	dBus:	inout STD_LOGIC_VECTOR(wordSize-1 downto 0);
	pcX, iarX : out std_logic_vector(wordSize-1 downto 0);
	iregX, accX, aluX : out std_logic_vector(wordSize-1 downto 0));
end component;

signal mem_en, mem_rw: STD_LOGIC;
signal aBus, dBus: STD_LOGIC_VECTOR(15 downto 0);
signal pc, ireg, iar, acc, alu: std_logic_vector(31 downto 0);

begin
	ramC: ram port map(reset, mem_en, mem_rw, aBus, dBus);
	cpuC: cpu port map(clk, reset, mem_en, mem_rw, aBus, dBus,
			pc, iar, ireg, acc, alu);
	mem_enX <= mem_en; mem_rwX <= mem_rw;
	aBusX <= aBus; dBusX <= dBus;
	pcX <= pc; iregX <= ireg; iarX <= iar; accX <= acc; aluX <= alu;
end topArch;