__projnav.log

vhdl经典源代码——键盘接口设计

Device Utilization Summary:

   Number of External IOBs            20 out of 141    14%
      Number of LOCed IOBs            20 out of 20    100%

   Number of Slices                    4 out of 3584    1%
      Number of SLICEMs                0 out of 1792    0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

WARNING:Par:276 - The signal clk_IBUF has no load
WARNING:Par:276 - The signal rst_IBUF has no load

Starting Placer

Phase 1.1
Phase 1.1 (Checksum:9896af) REAL time: 3 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 3 secs 

Phase 3.2


Phase 3.2 (Checksum:1c9c37d) REAL time: 3 secs 

Phase 4.8
.
Phase 4.8 (Checksum:98bd67) REAL time: 3 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 3 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 3 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 3 secs 

Writing design to file dial1.ncd


Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 2 secs 

Starting Router

Phase 1: 42 unrouted;       REAL time: 3 secs 

Phase 2: 36 unrouted;       REAL time: 3 secs 

Phase 3: 15 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted;       REAL time: 3 secs 


Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 3 secs 

Generating "PAR" statistics.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 4 secs 
Total CPU time to PAR completion: 3 secs 

Peak Memory Usage:  75 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 2
Number of info messages: 1

Writing design to file dial1.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s400.nph' in environment
D:/Xilinx.
   "dial1" is an NCD, version 3.1, device xc3s400, package pq208, speed -5

Analysis completed Thu Feb 23 12:54:47 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 4 secs 







Started process "Generate Programming File".

WARNING:PhysDesignRules:367 - The signal <clk_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <rst_IBUF> is incomplete. The signal
   does not drive any load pins in the design.


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Started process "Generate Programming File".

WARNING:PhysDesignRules:367 - The signal <clk_IBUF> is incomplete. The signal
   does not drive any load pins in the design.
WARNING:PhysDesignRules:367 - The signal <rst_IBUF> is incomplete. The signal
   does not drive any load pins in the design.


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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3215 - Unit work/DIAL1 is now defined in a different file: was E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/Dial/dial1.vhd, now is E:/temp/sp3-U/UE Basic Board/VHDL/Dial/dial1.vhd
WARNING:HDLParsers:3215 - Unit work/DIAL1/ARCH is now defined in a different file: was E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/Dial/dial1.vhd, now is E:/temp/sp3-U/UE Basic Board/VHDL/Dial/dial1.vhd
Compiling vhdl file "E:/temp/sp3-U/UE Basic Board/VHDL/Dial/dial1.vhd" in Library work.
Entity <dial1> compiled.
ERROR:HDLParsers:3384 - "E:/temp/sp3-U/UE Basic Board/VHDL/Dial/dial1.vhd" Line 24. String literal "00001" is not of size 6.
ERROR:HDLParsers:164 - "E:/temp/sp3-U/UE Basic Board/VHDL/Dial/dial1.vhd" Line 40. parse error, unexpected IDENTIFIER, expecting WHEN
--> 

Total memory usage is 66520 kilobytes

Number of errors   :    2 (   0 filtered)
Number of warnings :    2 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/temp/sp3-U/UE Basic Board/VHDL/Dial/dial1.vhd" in Library work.
Entity <dial1> compiled.
ERROR:HDLParsers:164 - "E:/temp/sp3-U/UE Basic Board/VHDL/Dial/dial1.vhd" Line 40. parse error, unexpected IDENTIFIER, expecting WHEN
--> 

Total memory usage is 66520 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/temp/sp3-U/UE Basic Board/VHDL/Dial/dial1.vhd" in Library work.
Entity <dial1> compiled.
ERROR:HDLParsers:164 - "E:/temp/sp3-U/UE Basic Board/VHDL/Dial/dial1.vhd" Line 39. parse error, unexpected WITH
--> 

Total memory usage is 66520 kilobytes

Number of errors   :    1 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/temp/sp3-U/UE Basic Board/VHDL/Dial/dial1.vhd" in Library work.
Entity <dial1> compiled.
Entity <dial1> (Architecture <arch>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <dial1> (Architecture <arch>).
Entity <dial1> analyzed. Unit <dial1> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <dial1>.
    Related source file is "E:/temp/sp3-U/UE Basic Board/VHDL/Dial/dial1.vhd".
    Found 16x8-bit ROM for signal <qout>.
    Found 16-bit up counter for signal <cnt_scan>.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Counter(s).
Unit <dial1> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 16x8-bit ROM                      : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <dial1> ...
Loading device for application Rf_Device from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block dial1, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-5 

 Number of Slices:                       4  out of   3584     0%  
 Number of 4 input LUTs:                 7  out of   7168     0%  
 Number of bonded IOBs:                 20  out of    141    14%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
No clock signals found in this design

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: 7.985ns

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd "e:\temp\sp3-u\ue basic
board\vhdl\dial/_ngo" -uc dial1.ucf -p xc3s400-pq208-5 dial1.ngc dial1.ngd 

Reading NGO file 'E:/temp/sp3-U/UE Basic Board/VHDL/Dial/dial1.ngc' ...

Applying constraints in "dial1.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "dial1.ngd" ...

Writing NGDBUILD log file "dial1.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s400pq208-5".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    4
Logic Utilization:
  Number of 4 input LUTs:               7 out of   7,168    1%
Logic Distribution:
  Number of occupied Slices:                            4 out of   3,584    1%
    Number of Slices containing only related logic:       4 out of       4  100%
    Number of Slices containing unrelated logic:          0 out of       4    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:           7 out of   7,168    1%
  Number of bonded IOBs:               20 out of     141   14%

Total equivalent gate count for design:  42
Additional JTAG gate count for IOBs:  960
Peak Memory Usage:  101 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "dial1_map.mrp" for details.




Started process "Place & Route".




Constraints file: dial1.pcf.
Loading device for application Rf_Device from file '3s400.nph' in environment
D:/Xilinx.
   "dial1" is an NCD, version 3.1, device xc3s400, package pq208, speed -5

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "ADVANCED 1.35 2005-01-22".