📄 __projnav.log
字号:
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "E:/temp/95144/vhdl/Dial/dial1.vhd" in Library work.Entity <dial1> compiled.Entity <dial1> (Architecture <arch>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <dial1> (Architecture <arch>).INFO:Xst:1561 - "E:/temp/95144/vhdl/Dial/dial1.vhd" line 90: Mux is complete : default of case is discardedEntity <dial1> analyzed. Unit <dial1> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <dial1>. Related source file is "E:/temp/95144/vhdl/Dial/dial1.vhd". Found 16x8-bit ROM for signal <dataout_xhdl1>. Found 16-bit up counter for signal <cnt_scan>. Found 2-bit register for signal <en_xhdl>. Summary: inferred 1 ROM(s). inferred 1 Counter(s). inferred 2 D-type flip-flop(s).Unit <dial1> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 1 16x8-bit ROM : 1# Counters : 1 16-bit up counter : 1# Registers : 2 1-bit register : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <dial1> ...
Started process "Translate".Extracting independent architecture files...Release 7.1.04i - ngdbuild H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc dial1.ucf -p xc9500xl dial1.ngc dial1.ngd Reading NGO file 'E:/temp/95144/vhdl/Dial/dial1.ngc' ...Applying constraints in "dial1.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "dial1.ngd" ...Writing NGDBUILD log file "dial1.bld"...NGDBUILD done.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "E:/temp/95144/vhdl/Dial/dial1.vhd" in Library work.Architecture arch of Entity dial1 is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <dial1> (Architecture <arch>).INFO:Xst:1561 - "E:/temp/95144/vhdl/Dial/dial1.vhd" line 90: Mux is complete : default of case is discardedEntity <dial1> analyzed. Unit <dial1> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <dial1>. Related source file is "E:/temp/95144/vhdl/Dial/dial1.vhd". Found 16x8-bit ROM for signal <dataout_xhdl1>. Found 16-bit up counter for signal <cnt_scan>. Found 2-bit register for signal <en_xhdl>. Summary: inferred 1 ROM(s). inferred 1 Counter(s). inferred 2 D-type flip-flop(s).Unit <dial1> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 1 16x8-bit ROM : 1# Counters : 1 16-bit up counter : 1# Registers : 2 1-bit register : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <dial1> ...
Started process "Translate".Release 7.1.04i - ngdbuild H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc dial1.ucf -p xc9500xl dial1.ngc dial1.ngd Reading NGO file 'E:/temp/95144/vhdl/Dial/dial1.ngc' ...Applying constraints in "dial1.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "dial1.ngd" ...Writing NGDBUILD log file "dial1.bld"...NGDBUILD done.
Started process "Fit".Release 7.1.04i - CPLD Optimizer/Partitioner H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Considering device XC95144XL-10-TQ144.Flattening design..Timing optimizationTiming driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 32 equations into 8 function blocks.WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6, because too many function block product terms are required. Buffering output signal dataout<7> to allow all signals assigned to this function block to be placed.WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6, because too many function block product terms are required. Buffering output signal dataout<4> to allow all signals assigned to this function block to be placed.WARNING:Cpld:896 - Unable to map all desired signals into function block, FB6, because too many function block product terms are required. Buffering output signal dataout<2> to allow all signals assigned to this function block to be placed........................Design dial1 has been optimized and fit into device XC95144XL-10-TQ144.
Started process "Generate Programming File".Release 7.1.04i - Programming File Generator H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Started process "Generate Timing".Release 7.1.04i - Timing Report Generator H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Note: This design contains no timing constraints.Note: A default set of constraints using a delay of 0.000ns will be used foranalysis.WARNING:Cpld:310 - Cannot apply TIMESPEC TS1001 = PERIOD:PERIOD_cnt_scan<15>.Q:0.000 nS because of one of the following: (a) a signal name was not found; (b) a signal was removed or renamed due to optimization; (c) there is no path between the FROM node and TO node in the TIMESPEC.Path tracing ......The number of paths traced: 263..The number of paths traced: 527.Checking for asynchronous logic...No asynchronous logic found.Generating TA GUI report ...Generating detailed paths report ...e:\temp\95144\vhdl\dial/dial1_html/tim/timing_report.htm has been created.
Started process "Generate HTML report".Release 7.1.04i - CPLD HTML Report Processor H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================WARNING:HDLParsers:3215 - Unit work/DIAL1 is now defined in a different file: was E:/temp/95144/vhdl/Dial/dial1.vhd, now is E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/Dial/dial1.vhdWARNING:HDLParsers:3215 - Unit work/DIAL1/ARCH is now defined in a different file: was E:/temp/95144/vhdl/Dial/dial1.vhd, now is E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/Dial/dial1.vhdCompiling vhdl file "E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/Dial/dial1.vhd" in Library work.Entity <dial1> compiled.Entity <dial1> (Architecture <arch>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <dial1> (Architecture <arch>).INFO:Xst:1561 - "E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/Dial/dial1.vhd" line 72: Mux is complete : default of case is discardedEntity <dial1> analyzed. Unit <dial1> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <dial1>. Related source file is "E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/Dial/dial1.vhd".WARNING:Xst:1780 - Signal <en_xhdl> is never used or assigned. Found 16x8-bit ROM for signal <dataout_xhdl1>. Found 16-bit up counter for signal <cnt_scan>. Summary: inferred 1 ROM(s). inferred 1 Counter(s).Unit <dial1> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 1 16x8-bit ROM : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <dial1> ...Loading device for application Rf_Device from file '3s400.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block dial1, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 3s400pq208-5 Number of Slices: 4 out of 3584 0% Number of 4 input LUTs: 7 out of 7168 0% Number of bonded IOBs: 20 out of 141 14% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 7.985ns=========================================================================
Started process "Translate".Command Line: ngdbuild -intstyle ise -dde:\cindy\working\ue_extboard\sp3\vhdl\dial/_ngo -nt timestamp -uc dial1.ucf -pxc3s400-pq208-5 dial1.ngc dial1.ngd Reading NGO file 'E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/Dial/dial1.ngc' ...Applying constraints in "dial1.ucf" to the design...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "dial1.ngd" ...Writing NGDBUILD log file "dial1.bld"...NGDBUILD done.
Started process "Map".Using target part "3s400pq208-5".Mapping design into LUTs...ERROR:MapLib:30 - LOC constraint p66 on datain<1> is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.ERROR:MapLib:30 - LOC constraint p69 on datain<0> is invalid: No such site on the device. To bypass this error set the environment variable 'XIL_MAP_LOCWARN'.Error found in mapping process, exiting...Errors found during the mapping phase. Please see map report file for moredetails. Output files will not be written.Design Summary--------------⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -