ps2.vhd

vhdl经典源代码——ps2接口设计

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

ENTITY ps2 IS
	PORT (kb_data,kb_clk : IN  std_logic;
			en: OUT std_logic;
			dataout: OUT std_logic_vector(6 downto 0);
			led: OUT std_logic_vector(7 downto 0)
	);
END ps2;

ARCHITECTURE ps2_arch OF ps2 IS
signal master,slave:std_logic_vector(9 downto 0);

BEGIN
	
	en<='0';
	masterp:
	process (kb_clk)
	begin
	  if (kb_clk'event and kb_clk='0') then
		master<=kb_data & slave(9 downto 1);
		end if;
	end process masterp;
	slavep:
	process (kb_clk,slave)
	begin
	  if (kb_clk'event and kb_clk='1') then
		slave<=master;
	end if;
	led<=not (slave(7 downto 0));
	case slave(7 downto 0) is
		when"00010110"=>dataout<="1101101";
		when"00011110"=>dataout<="0100010";
		when"00100110"=>dataout<="0100100";
		when"00100101"=>dataout<="1000101";
		when"00101110"=>dataout<="0010100";
		when"00110110"=>dataout<="0010000";
		when"00111101"=>dataout<="0101101";
		when"00111110"=>dataout<="0000000";
		when"01000110"=>dataout<="0000100";
		when"01000101"=>dataout<="0001000";
		when others=>dataout<="0000000";

	end case;
end process slavep;
end ps2_arch;