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vhdl经典源代码——ps2接口设计

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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/PS2/ps2.vhd" in Library work.
Entity <ps2> compiled.
Entity <ps2> (Architecture <ps2_arch>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <ps2> (Architecture <ps2_arch>).
Entity <ps2> analyzed. Unit <ps2> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <ps2>.
    Related source file is "E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/PS2/ps2.vhd".
    Found 10-bit register for signal <master>.
    Found 10-bit register for signal <slave>.
    Summary:
	inferred  20 D-type flip-flop(s).
Unit <ps2> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
 10-bit register                   : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <ps2> ...
Loading device for application Rf_Device from file '3s400.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block ps2, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s400pq208-4 

 Number of Slices:                      13  out of   3584     0%  
 Number of Slice Flip Flops:            20  out of   7168     0%  
 Number of 4 input LUTs:                22  out of   7168     0%  
 Number of bonded IOBs:                 18  out of    141    12%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
kb_clk                             | BUFGP                  | 20    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 4.134ns (Maximum Frequency: 241.896MHz)
   Minimum input arrival time before clock: 1.825ns
   Maximum output required time after clock: 15.288ns
   Maximum combinational path delay: No path found

=========================================================================




Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
e:\cindy\working\ue_extboard\sp3\vhdl\ps2/_ngo -nt timestamp -uc ps2.ucf -p
xc3s400-pq208-4 ps2.ngc ps2.ngd 

Reading NGO file 'E:/Cindy/working/UE_EXTBOARD/SP3/VHDL/PS2/ps2.ngc' ...

Applying constraints in "ps2.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "ps2.ngd" ...

Writing NGDBUILD log file "ps2.bld"...

NGDBUILD done.




Started process "Map".

Using target part "3s400pq208-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:          19 out of   7,168    1%
  Number of 4 input LUTs:              22 out of   7,168    1%
Logic Distribution:
  Number of occupied Slices:                           22 out of   3,584    1%
    Number of Slices containing only related logic:      22 out of      22  100%
    Number of Slices containing unrelated logic:          0 out of      22    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:          22 out of   7,168    1%
  Number of bonded IOBs:               18 out of     141   12%
    IOB Flip Flops:                     1
  Number of GCLKs:                     1 out of       8   12%

Total equivalent gate count for design:  295
Additional JTAG gate count for IOBs:  864
Peak Memory Usage:  101 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "ps2_map.mrp" for details.




Started process "Place & Route".




Constraints file: ps2.pcf.
Loading device for application Rf_Device from file '3s400.nph' in environment
D:/Xilinx.
   "ps2" is an NCD, version 3.1, device xc3s400, package pq208, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.37 2005-07-22".


Device Utilization Summary:

   Number of BUFGMUXs                  1 out of 8      12%
   Number of External IOBs            18 out of 141    12%
      Number of LOCed IOBs            18 out of 18    100%

   Number of Slices                   22 out of 3584    1%
      Number of SLICEMs                0 out of 1792    0%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:9896fa) REAL time: 2 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 2 secs 

Phase 3.2
.....
.........


Phase 3.2 (Checksum:98b485) REAL time: 2 secs 

Phase 4.8
.
Phase 4.8 (Checksum:9956af) REAL time: 2 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 2 secs 

Phase 6.18
Phase 6.18 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file ps2.ncd


Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 2 secs 

Starting Router

Phase 1: 126 unrouted;       REAL time: 2 secs 

Phase 2: 115 unrouted;       REAL time: 3 secs 

Phase 3: 33 unrouted;       REAL time: 3 secs 

Phase 4: 0 unrouted;       REAL time: 3 secs 


Total REAL time to Router completion: 3 secs 
Total CPU time to Router completion: 3 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|        kb_clk_BUFGP |      BUFGMUX0| No   |   11 |  0.059     |  1.073      |
+---------------------+--------------+------+------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 3 secs 
Total CPU time to PAR completion: 3 secs 

Peak Memory Usage:  74 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file ps2.ncd



PAR done!

Started process "Generate Post-Place & Route Static Timing".

Loading device for application Rf_Device from file '3s400.nph' in environment
D:/Xilinx.
   "ps2" is an NCD, version 3.1, device xc3s400, package pq208, speed -4

Analysis completed Wed Feb 22 15:08:15 2006
--------------------------------------------------------------------------------

Generating Report ...

Number of warnings: 0
Total time: 3 secs 


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