fsm.v

Verilog_HDL源码 Verilog_HDL源码

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//FSM.v
module FSM (DUTY_CYC, PRESET_N, PCLK, PADDR, PWDATA);

    input PCLK, PRESET_N;
    input [2:0] DUTY_CYC;

    output [4:0] PADDR;
    output [7:0] PWDATA;

    reg [4:0] PADDR;
    reg [7:0] PWDATA;

    parameter /* Configuration States of FSM */
                S_RESET = 3'b000,
                S_CONFIG_PRE = 3'b001,
                S_CONFIG_PER = 3'b010,  
                S_CONFIG_EN = 3'b011,
                S_CONFIG_MASK = 3'b100,
                S_RUN_POS = 3'b101,
                S_RUN_NEG = 3'b110;
    reg [2:0] STATE;
    
    parameter PRESCALE = 8'b0001;   /* PRESCALE=1 */
    parameter PERIOD = 8'b1110;     /* PERIOD=14 */
    parameter PWM_ENABLE = 8'b0001; /* PWM_ENABLE=1 */
    parameter INT_MASK = 8'b0000;

    always @(posedge PCLK)
        begin: FSM_CORE
            if (!PRESET_N)
                STATE = S_RESET;
            case (STATE)
                S_RESET: 
                    if (PRESET_N)
                        STATE = S_CONFIG_PRE;

                S_CONFIG_PRE: /*PRESCALE Register Configuration*/
                    begin
                        PADDR = 5'b000;
                        PWDATA = PRESCALE;
                        STATE = S_CONFIG_PER;
                    end
                S_CONFIG_PER: /*PERIOD Register Configuration*/
                    begin
                        PADDR = 5'b001;
                        PWDATA = PERIOD;
                        STATE = S_CONFIG_EN;
                    end
                S_CONFIG_EN: /*CorePWM Enable Register Configuration*/
                    begin
                        PADDR = 5'b010;
                        PWDATA = PWM_ENABLE;
                        STATE = S_CONFIG_MASK;
                    end
                S_CONFIG_MASK: /*INT Register Configuration*/
                    begin
                        PADDR = 5'b011;
                        PWDATA = INT_MASK;
                        STATE = S_RUN_POS;
                    end
                S_RUN_POS: /*Positive Edge Register Configuration*/
                    begin
                        PADDR = 5'b101;
                        case (DUTY_CYC)
                            /*For Register Values based on Duty Cycle Input, refer to Table 2*/
                            3'b000: PWDATA = 8'b1111;
                            3'b001: PWDATA = 8'b0000;
                            3'b010: PWDATA = 8'b0000;
                            3'b011: PWDATA = 8'b0000;
                            3'b100: PWDATA = 8'b0000;
                            3'b101: PWDATA = 8'b0000;
                        endcase
                        STATE = S_RUN_NEG;
                    end
                S_RUN_NEG: /*Negative Edge Register Configuration*/
                    begin
                        PADDR = 5'b110;
                        case (DUTY_CYC)
                            /*For Register Values based on Duty Cycle Input, refer to Table 2*/
                            3'b000: PWDATA = 8'b0000;
                            3'b001: PWDATA = 8'b0011;
                            3'b010: PWDATA = 8'b0110;
                            3'b011: PWDATA = 8'b1001;
                            3'b100: PWDATA = 8'b1100;
                            3'b101: PWDATA = 8'b1111;
                        endcase
                        STATE = S_RUN_POS;                    
                    end
            endcase
        end
endmodule