fsm_corepwm.v

Verilog_HDL源码 Verilog_HDL源码

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// FSM_CorePWM.v

module FSM_CorePWM #(
parameter PWM_NUM = 1)
(PCLK, PRESET_N, PSEL, PENABLE, PWRITE, DUTY_CYC, PWM, PRDATA, INT);

    input PCLK, PRESET_N, PSEL, PENABLE, PWRITE;
    input [2:0] DUTY_CYC;
    
    output [PWM_NUM:1] PWM;
    output [7:0] PRDATA;
    output INT;

    wire [4:0] PADDR_TOP;
    wire [7:0] PWDATA_TOP;

    FSM FSM_TOP (.PCLK(PCLK),.PRESET_N(PRESET_N),.DUTY_CYC(DUTY_CYC),
                .PADDR(PADDR_TOP[4:0]),.PWDATA(PWDATA_TOP[7:0]));
    corepwm #(.PWM_NUM(PWM_NUM))
	COREPWM_TOP (.PCLK(PCLK),.PRESET_N(PRESET_N),.PSEL(PSEL),.PENABLE(PENABLE),.PWRITE(PWRITE),
                .PADDR(PADDR_TOP[4:0]),.PWDATA(PWDATA_TOP[7:0]),.PWM(PWM),.PRDATA(PRDATA[7:0]),.INT(INT));
endmodule