iis_vhdl.tan.qmsg

VHDL实现了IIS接口程序

{ "Info" "ITDB_FULL_TCO_RESULT" "CS5340_SCLK DATAOUT\[16\] CS5340_Data\[16\] 15.914 ns register " "Info: tco from clock \"CS5340_SCLK\" to destination pin \"DATAOUT\[16\]\" through register \"CS5340_Data\[16\]\" is 15.914 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CS5340_SCLK source 10.172 ns + Longest register " "Info: + Longest clock path from clock \"CS5340_SCLK\" to source register is 10.172 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CS5340_SCLK 1 CLK PIN_70 31 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_70; Fanout = 31; CLK Node = 'CS5340_SCLK'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CS5340_SCLK } "NODE_NAME" } } { "IIS_VHDL.vhd" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/IIS_VHDL.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.992 ns) + CELL(0.711 ns) 10.172 ns CS5340_Data\[16\] 2 REG LC_X17_Y7_N2 3 " "Info: 2: + IC(7.992 ns) + CELL(0.711 ns) = 10.172 ns; Loc. = LC_X17_Y7_N2; Fanout = 3; REG Node = 'CS5340_Data\[16\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.703 ns" { CS5340_SCLK CS5340_Data[16] } "NODE_NAME" } } { "IIS_VHDL.vhd" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/IIS_VHDL.vhd" 32 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 21.43 % ) " "Info: Total cell delay = 2.180 ns ( 21.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.992 ns ( 78.57 % ) " "Info: Total interconnect delay = 7.992 ns ( 78.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.172 ns" { CS5340_SCLK CS5340_Data[16] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.172 ns" { CS5340_SCLK CS5340_SCLK~out0 CS5340_Data[16] } { 0.000ns 0.000ns 7.992ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "IIS_VHDL.vhd" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/IIS_VHDL.vhd" 32 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.518 ns + Longest register pin " "Info: + Longest register to pin delay is 5.518 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000