iis_vhdl.tan.qmsg

VHDL实现了IIS接口程序

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLKIN register sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|safe_q\[1\] register sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|safe_q\[9\] 157.55 MHz 6.347 ns Internal " "Info: Clock \"CLKIN\" has Internal fmax of 157.55 MHz between source register \"sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|safe_q\[1\]\" and destination register \"sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|safe_q\[9\]\" (period= 6.347 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.086 ns + Longest register register " "Info: + Longest register to register delay is 6.086 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|safe_q\[1\] 1 REG LC_X12_Y8_N6 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y8_N6; Fanout = 13; REG Node = 'sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|safe_q\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1] } "NODE_NAME" } } { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 123 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.523 ns) + CELL(0.575 ns) 1.098 ns sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella1~COUTCOUT1_1 2 COMB LC_X12_Y8_N6 2 " "Info: 2: + IC(0.523 ns) + CELL(0.575 ns) = 1.098 ns; Loc. = LC_X12_Y8_N6; Fanout = 2; COMB Node = 'sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella1~COUTCOUT1_1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.098 ns" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1] sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella1~COUTCOUT1_1 } "NODE_NAME" } } { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.178 ns sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella2~COUTCOUT1_1 3 COMB LC_X12_Y8_N7 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.178 ns; Loc. = LC_X12_Y8_N7; Fanout = 2; COMB Node = 'sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella2~COUTCOUT1_1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella1~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella2~COUTCOUT1_1 } "NODE_NAME" } } { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 49 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.258 ns sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella3~COUTCOUT1_1 4 COMB LC_X12_Y8_N8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.258 ns; Loc. = LC_X12_Y8_N8; Fanout = 2; COMB Node = 'sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella3~COUTCOUT1_1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella2~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella3~COUTCOUT1_1 } "NODE_NAME" } } { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 57 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.516 ns sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella4~COUT 5 COMB LC_X12_Y8_N9 6 " "Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.516 ns; Loc. = LC_X12_Y8_N9; Fanout = 6; COMB Node = 'sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella4~COUT'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.258 ns" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella3~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella4~COUT } "NODE_NAME" } } { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 65 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.652 ns sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella9~COUT 6 COMB LC_X12_Y7_N4 1 " "Info: 6: + IC(0.000 ns) + CELL(0.136 ns) = 1.652 ns; Loc. = LC_X12_Y7_N4; Fanout = 1; COMB Node = 'sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella9~COUT'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella4~COUT sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella9~COUT } "NODE_NAME" } } { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 105 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.621 ns) 2.273 ns sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|cout 7 COMB LC_X12_Y7_N5 4 " "Info: 7: + IC(0.000 ns) + CELL(0.621 ns) = 2.273 ns; Loc. = LC_X12_Y7_N5; Fanout = 4; COMB Node = 'sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|cout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.621 ns" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella9~COUT sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|cout } "NODE_NAME" } } { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 152 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.251 ns) + CELL(0.114 ns) 3.638 ns sld_signaltap:IIS_VHDL\|comb~154 8 COMB LC_X12_Y8_N1 1 " "Info: 8: + IC(1.251 ns) + CELL(0.114 ns) = 3.638 ns; Loc. = LC_X12_Y8_N1; Fanout = 1; COMB Node = 'sld_signaltap:IIS_VHDL\|comb~154'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.365 ns" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|cout sld_signaltap:IIS_VHDL|comb~154 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.182 ns) + CELL(0.114 ns) 3.934 ns sld_signaltap:IIS_VHDL\|comb~155 9 COMB LC_X12_Y8_N2 10 " "Info: 9: + IC(0.182 ns) + CELL(0.114 ns) = 3.934 ns; Loc. = LC_X12_Y8_N2; Fanout = 10; COMB Node = 'sld_signaltap:IIS_VHDL\|comb~155'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.296 ns" { sld_signaltap:IIS_VHDL|comb~154 sld_signaltap:IIS_VHDL|comb~155 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.285 ns) + CELL(0.867 ns) 6.086 ns sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|safe_q\[9\] 10 REG LC_X12_Y7_N4 12 " "Info: 10: + IC(1.285 ns) + CELL(0.867 ns) = 6.086 ns; Loc. = LC_X12_Y7_N4; Fanout = 12; REG Node = 'sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|safe_q\[9\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.152 ns" { sld_signaltap:IIS_VHDL|comb~155 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[9] } "NODE_NAME" } } { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 123 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.845 ns ( 46.75 % ) " "Info: Total cell delay = 2.845 ns ( 46.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.241 ns ( 53.25 % ) " "Info: Total interconnect delay = 3.241 ns ( 53.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.086 ns" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1] sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella1~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella2~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella3~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella4~COUT sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella9~COUT sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|cout sld_signaltap:IIS_VHDL|comb~154 sld_signaltap:IIS_VHDL|comb~155 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.086 ns" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1] sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella1~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella2~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella3~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella4~COUT sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella9~COUT sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|cout sld_signaltap:IIS_VHDL|comb~154 sld_signaltap:IIS_VHDL|comb~155 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[9] } { 0.000ns 0.523ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.251ns 0.182ns 1.285ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.621ns 0.114ns 0.114ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN destination 2.740 ns + Shortest register " "Info: + Shortest clock path from clock \"CLKIN\" to destination register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLKIN 1 CLK PIN_10 328 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_10; Fanout = 328; CLK Node = 'CLKIN'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLKIN } "NODE_NAME" } } { "IIS_VHDL.vhd" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/IIS_VHDL.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.711 ns) 2.740 ns sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|safe_q\[9\] 2 REG LC_X12_Y7_N4 12 " "Info: 2: + IC(0.560 ns) + CELL(0.711 ns) = 2.740 ns; Loc. = LC_X12_Y7_N4; Fanout = 12; REG Node = 'sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|safe_q\[9\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.271 ns" { CLKIN sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[9] } "NODE_NAME" } } { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 123 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.56 % ) " "Info: Total cell delay = 2.180 ns ( 79.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 20.44 % ) " "Info: Total interconnect delay = 0.560 ns ( 20.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { CLKIN sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { CLKIN CLKIN~out0 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[9] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN source 2.740 ns - Longest register " "Info: - Longest clock path from clock \"CLKIN\" to source register is 2.740 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLKIN 1 CLK PIN_10 328 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_10; Fanout = 328; CLK Node = 'CLKIN'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLKIN } "NODE_NAME" } } { "IIS_VHDL.vhd" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/IIS_VHDL.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.711 ns) 2.740 ns sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|safe_q\[1\] 2 REG LC_X12_Y8_N6 13 " "Info: 2: + IC(0.560 ns) + CELL(0.711 ns) = 2.740 ns; Loc. = LC_X12_Y8_N6; Fanout = 13; REG Node = 'sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|safe_q\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.271 ns" { CLKIN sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1] } "NODE_NAME" } } { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 123 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 79.56 % ) " "Info: Total cell delay = 2.180 ns ( 79.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 20.44 % ) " "Info: Total interconnect delay = 0.560 ns ( 20.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { CLKIN sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { CLKIN CLKIN~out0 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { CLKIN sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { CLKIN CLKIN~out0 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[9] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { CLKIN sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { CLKIN CLKIN~out0 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 123 8 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 123 8 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.086 ns" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1] sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella1~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella2~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella3~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella4~COUT sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella9~COUT sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|cout sld_signaltap:IIS_VHDL|comb~154 sld_signaltap:IIS_VHDL|comb~155 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.086 ns" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1] sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella1~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella2~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella3~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella4~COUT sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella9~COUT sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|cout sld_signaltap:IIS_VHDL|comb~154 sld_signaltap:IIS_VHDL|comb~155 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[9] } { 0.000ns 0.523ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.251ns 0.182ns 1.285ns } { 0.000ns 0.575ns 0.080ns 0.080ns 0.258ns 0.136ns 0.621ns 0.114ns 0.114ns 0.867ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { CLKIN sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { CLKIN CLKIN~out0 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[9] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.740 ns" { CLKIN sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.740 ns" { CLKIN CLKIN~out0 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1] } { 0.000ns 0.000ns 0.560ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "sld_signaltap:IIS_VHDL\|acq_trigger_in_reg\[0\] CS5340_DOUT CLKIN 5.383 ns register " "Info: tsu for register \"sld_signaltap:IIS_VHDL\|acq_trigger_in_reg\[0\]\" (data pin = \"CS5340_DOUT\", clock pin = \"CLKIN\") is 5.383 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.128 ns + Longest pin register " "Info: + Longest pin to register delay is 8.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CS5340_DOUT 1 PIN PIN_71 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_71; Fanout = 25; PIN Node = 'CS5340_DOUT'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CS5340_DOUT } "NODE_NAME" } } { "IIS_VHDL.vhd" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/IIS_VHDL.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.544 ns) + CELL(0.115 ns) 8.128 ns sld_signaltap:IIS_VHDL\|acq_trigger_in_reg\[0\] 2 REG LC_X18_Y9_N1 3 " "Info: 2: + IC(6.544 ns) + CELL(0.115 ns) = 8.128 ns; Loc. = LC_X18_Y9_N1; Fanout = 3; REG Node = 'sld_signaltap:IIS_VHDL\|acq_trigger_in_reg\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.659 ns" { CS5340_DOUT sld_signaltap:IIS_VHDL|acq_trigger_in_reg[0] } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" 573 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.584 ns ( 19.49 % ) " "Info: Total cell delay = 1.584 ns ( 19.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.544 ns ( 80.51 % ) " "Info: Total interconnect delay = 6.544 ns ( 80.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.128 ns" { CS5340_DOUT sld_signaltap:IIS_VHDL|acq_trigger_in_reg[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.128 ns" { CS5340_DOUT CS5340_DOUT~out0 sld_signaltap:IIS_VHDL|acq_trigger_in_reg[0] } { 0.000ns 0.000ns 6.544ns } { 0.000ns 1.469ns 0.115ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" 573 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLKIN destination 2.782 ns - Shortest register " "Info: - Shortest clock path from clock \"CLKIN\" to destination register is 2.782 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns CLKIN 1 CLK PIN_10 328 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_10; Fanout = 328; CLK Node = 'CLKIN'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CLKIN } "NODE_NAME" } } { "IIS_VHDL.vhd" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/IIS_VHDL.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.602 ns) + CELL(0.711 ns) 2.782 ns sld_signaltap:IIS_VHDL\|acq_trigger_in_reg\[0\] 2 REG LC_X18_Y9_N1 3 " "Info: 2: + IC(0.602 ns) + CELL(0.711 ns) = 2.782 ns; Loc. = LC_X18_Y9_N1; Fanout = 3; REG Node = 'sld_signaltap:IIS_VHDL\|acq_trigger_in_reg\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.313 ns" { CLKIN sld_signaltap:IIS_VHDL|acq_trigger_in_reg[0] } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_signaltap.vhd" 573 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns ( 78.36 % ) " "Info: Total cell delay = 2.180 ns ( 78.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.602 ns ( 21.64 % ) " "Info: Total interconnect delay = 0.602 ns ( 21.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { CLKIN sld_signaltap:IIS_VHDL|acq_trigger_in_reg[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { CLKIN CLKIN~out0 sld_signaltap:IIS_VHDL|acq_trigger_in_reg[0] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.128 ns" { CS5340_DOUT sld_signaltap:IIS_VHDL|acq_trigger_in_reg[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.128 ns" { CS5340_DOUT CS5340_DOUT~out0 sld_signaltap:IIS_VHDL|acq_trigger_in_reg[0] } { 0.000ns 0.000ns 6.544ns } { 0.000ns 1.469ns 0.115ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.782 ns" { CLKIN sld_signaltap:IIS_VHDL|acq_trigger_in_reg[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.782 ns" { CLKIN CLKIN~out0 sld_signaltap:IIS_VHDL|acq_trigger_in_reg[0] } { 0.000ns 0.000ns 0.602ns } { 0.000ns 1.469ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}