iis_vhdl.fit.qmsg

VHDL实现了IIS接口程序

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Info: Fitter placement operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.469 ns register register " "Info: Estimated most critical path is register to register delay of 6.469 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|safe_q\[0\] 1 REG LAB_X12_Y8 37 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X12_Y8; Fanout = 37; REG Node = 'sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|safe_q\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[0] } "NODE_NAME" } } { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 123 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.461 ns) + CELL(0.575 ns) 1.036 ns sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella0~COUTCOUT1_1 2 COMB LAB_X12_Y8 2 " "Info: 2: + IC(0.461 ns) + CELL(0.575 ns) = 1.036 ns; Loc. = LAB_X12_Y8; Fanout = 2; COMB Node = 'sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella0~COUTCOUT1_1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.036 ns" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[0] sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella0~COUTCOUT1_1 } "NODE_NAME" } } { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 34 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.116 ns sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella1~COUTCOUT1_1 3 COMB LAB_X12_Y8 2 " "Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.116 ns; Loc. = LAB_X12_Y8; Fanout = 2; COMB Node = 'sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella1~COUTCOUT1_1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella0~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella1~COUTCOUT1_1 } "NODE_NAME" } } { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 41 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.196 ns sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella2~COUTCOUT1_1 4 COMB LAB_X12_Y8 2 " "Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.196 ns; Loc. = LAB_X12_Y8; Fanout = 2; COMB Node = 'sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella2~COUTCOUT1_1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella1~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella2~COUTCOUT1_1 } "NODE_NAME" } } { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 49 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 1.276 ns sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella3~COUTCOUT1_1 5 COMB LAB_X12_Y8 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 1.276 ns; Loc. = LAB_X12_Y8; Fanout = 2; COMB Node = 'sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella3~COUTCOUT1_1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella2~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella3~COUTCOUT1_1 } "NODE_NAME" } } { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 57 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 1.534 ns sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella4~COUT 6 COMB LAB_X12_Y8 6 " "Info: 6: + IC(0.000 ns) + CELL(0.258 ns) = 1.534 ns; Loc. = LAB_X12_Y8; Fanout = 6; COMB Node = 'sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella4~COUT'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.258 ns" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella3~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella4~COUT } "NODE_NAME" } } { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 65 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.670 ns sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella9~COUT 7 COMB LAB_X12_Y7 1 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 1.670 ns; Loc. = LAB_X12_Y7; Fanout = 1; COMB Node = 'sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|counter_cella9~COUT'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella4~COUT sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella9~COUT } "NODE_NAME" } } { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 105 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.679 ns) 2.349 ns sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|cout 8 COMB LAB_X12_Y7 4 " "Info: 8: + IC(0.000 ns) + CELL(0.679 ns) = 2.349 ns; Loc. = LAB_X12_Y7; Fanout = 4; COMB Node = 'sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|cout'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.679 ns" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella9~COUT sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|cout } "NODE_NAME" } } { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 152 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.094 ns) + CELL(0.292 ns) 3.735 ns sld_signaltap:IIS_VHDL\|comb~154 9 COMB LAB_X12_Y8 1 " "Info: 9: + IC(1.094 ns) + CELL(0.292 ns) = 3.735 ns; Loc. = LAB_X12_Y8; Fanout = 1; COMB Node = 'sld_signaltap:IIS_VHDL\|comb~154'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.386 ns" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|cout sld_signaltap:IIS_VHDL|comb~154 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.265 ns) + CELL(0.442 ns) 4.442 ns sld_signaltap:IIS_VHDL\|comb~155 10 COMB LAB_X12_Y8 10 " "Info: 10: + IC(0.265 ns) + CELL(0.442 ns) = 4.442 ns; Loc. = LAB_X12_Y8; Fanout = 10; COMB Node = 'sld_signaltap:IIS_VHDL\|comb~155'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.707 ns" { sld_signaltap:IIS_VHDL|comb~154 sld_signaltap:IIS_VHDL|comb~155 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.160 ns) + CELL(0.867 ns) 6.469 ns sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|safe_q\[9\] 11 REG LAB_X12_Y7 36 " "Info: 11: + IC(1.160 ns) + CELL(0.867 ns) = 6.469 ns; Loc. = LAB_X12_Y7; Fanout = 36; REG Node = 'sld_signaltap:IIS_VHDL\|sld_acquisition_buffer:sld_acquisition_buffer_inst\|lpm_counter:\\write_address_non_zero_gen:write_pointer_counter\|cntr_fgh:auto_generated\|safe_q\[9\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.027 ns" { sld_signaltap:IIS_VHDL|comb~155 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[9] } "NODE_NAME" } } { "db/cntr_fgh.tdf" "" { Text "D:/PROJECT/arm9_develop/Programs/IIS_VHDL/db/cntr_fgh.tdf" 123 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.489 ns ( 53.93 % ) " "Info: Total cell delay = 3.489 ns ( 53.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.980 ns ( 46.07 % ) " "Info: Total interconnect delay = 2.980 ns ( 46.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.469 ns" { sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[0] sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella0~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella1~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella2~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella3~COUTCOUT1_1 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella4~COUT sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|counter_cella9~COUT sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|cout sld_signaltap:IIS_VHDL|comb~154 sld_signaltap:IIS_VHDL|comb~155 sld_signaltap:IIS_VHDL|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[9] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "6 8 " "Info: Average interconnect usage is 6% of the available device resources. Peak interconnect usage is 8%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x14_y0 x27_y14 " "Info: The peak interconnect region extends from location x14_y0 to location x27_y14" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:03 " "Info: Fitter routing operations ending: elapsed time is 00:00:03" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}