iis_vhdl.tan.rpt

VHDL实现了IIS接口程序

; Device Name                                           ; EP1C3T100C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                          ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CS5340_SCLK                  ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; CLKIN                        ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CS5340_SCLK'                                                                                                                                                                                 ;
+-------+------------------------------------------------+-----------------+-----------------+-------------+-------------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From            ; To              ; From Clock  ; To Clock    ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------------+-----------------+-------------+-------------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; LRCK            ; CS5340_Data[14] ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 3.137 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; DNUM[3]~reg0    ; CS5340_Data[17] ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 3.019 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; DNUM[3]~reg0    ; CS5340_Data[21] ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 3.019 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; DNUM[3]~reg0    ; CS5340_Data[23] ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 3.017 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; DNUM[3]~reg0    ; CS5340_Data[20] ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 3.007 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; DNUM[3]~reg0    ; CS5340_Data[16] ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 3.003 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; DNUM[3]~reg0    ; CS5340_Data[7]  ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 3.000 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; DNUM[3]~reg0    ; CS5340_Data[5]  ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 2.997 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; DNUM[3]~reg0    ; CS5340_Data[18] ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 2.997 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; DNUM[0]~reg0    ; CS5340_Data[14] ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 2.990 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; DNUM[3]~reg0    ; CS5340_Data[1]  ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 2.989 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; DNUM[3]~reg0    ; CS5340_Data[22] ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 2.988 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; LRCK            ; CS5340_Data[4]  ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 2.978 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; LRCK            ; CS5340_Data[6]  ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 2.977 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; LRCK            ; CS5340_Data[2]  ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 2.973 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; LRCK            ; CS5340_Data[15] ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 2.950 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; LRCK            ; CS5340_Data[11] ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 2.948 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; LRCK            ; CS5340_Data[13] ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 2.945 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; LRCK            ; CS5340_Data[12] ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 2.931 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; LRCK            ; CS5340_Data[10] ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 2.930 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; DNUM[3]~reg0    ; CS5340_Data[14] ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 2.887 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; DNUM[2]~reg0    ; CS5340_Data[6]  ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 2.847 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; DNUM[2]~reg0    ; CS5340_Data[15] ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 2.846 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; DNUM[0]~reg0    ; CS5340_Data[4]  ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 2.825 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; DNUM[0]~reg0    ; CS5340_Data[6]  ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 2.824 ns                ;
; N/A   ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; DNUM[0]~reg0    ; CS5340_Data[2]  ; CS5340_SCLK ; CS5340_SCLK ; None                        ; None                      ; 2.820 ns                ;