changmaiwei.vhd

应用vhdl语言进行加法器的设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity changmaiwei is 
 port(clk,en:in std_logic;
      long:out std_logic);
end changmaiwei;
architecture bh of changmaiwei is
begin 
 process(clk,en)
  variable sum:std_logic_vector(2 downto 0);
begin 
 if en='0'then                --清零
    sum:="000" ;
 else 
   if rising_edge(clk) then
       sum :=sum+'1';       --计数
      if sum>4 then       
         long<='1'; 
      else 
         long<='0'; 
      end if;
   end if;
 end if;
end process;
end bh;