time60.v

来自「用VHDL写的运动计时表程序」· Verilog 代码 · 共 58 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:28:56 10/29/2006 
// Design Name: 
// Module Name:    time60 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module time60(cin, cin_min, load, clr, out_min, data_min);
    output [0:0] cin;
    input [0:0] cin_min;
    input [0:0] load;
    input [0:0] clr;
    output [7:0] out_min;
    input [7:0] data_min;
	 reg [7:0] out_min;
	 reg cin;
	 
    always @(posedge cin_min or posedge load or negedge clr)
	 begin
	   cin<=0;
	  if(!clr) 
	    out_min<=0;
	  else if(load)
	    out_min<=data_min;
	  else 
	    begin
	      if(out_min[3:0]==4'd9)
	        begin
			    if(out_min[7:4]>=4'd5)
				   begin
					  cin<=1;
					  out_min<=0;
					end
				 else
				   begin
					  out_min[7:4]<=out_min[7:4]+1;
					  out_min[3:0]<=0;
					end
			  end			  
         else  
	        out_min<=out_min+1;
		 end
	  end
endmodule