free_change.vhdl

来自「本代码介绍了使用VHDL开发FPGA的一般流程」· VHDL 代码 · 共 36 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Free_Change is
	 Generic (  rate : integer :=10  );
	 Port(
	 		clk_in 		:in STD_LOGIC;				--输入时钟脉冲
			clk_out		:out STD_LOGIC				--输出时钟脉冲
	 );
end Free_Change;

architecture Behavioral of Free_Change is
 			attribute clock_buffer:string;
		  	attribute clock_buffer of clk_in :signal is"ibuf";
			signal count :integer  range 0 to rate:=1;	
begin
	Process(clk_in)								--按rate记数
	begin
	If clk_in'event and clk_in='1' then
		If count<rate  then
			   	clk_out<='0';			
				count<=count+1; 
		Else		   		   	     
				clk_out<='1';
				count<=1;
		end If;
	End If;	  
	End process;
End Behavioral;