counter10.vhdl

来自「本代码介绍了使用VHDL开发FPGA的一般流程」· VHDL 代码 · 共 49 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter10 is
PORT(
	Reset,CLK  		:IN STD_LOGIC;	
	carry_out  		:OUT STD_LOGIC;	
	count_BCD_out 		:OUT STD_LOGIC_VECTOR(3 downto 0)
	);
end counter10;

architecture Behavioral of counter10 is

Signal Q					:STD_LOGIC_VECTOR(3 downto 0);
begin
	PROCESS(CLK,Reset)
	begin
		If Reset='0'	then
			Q<="0000";				
		elsif falling_edge(CLK)	then
				if Q<9	then
					Q <= Q+1;
				else		Q<="0000";
				end if;
		end if;
	end process;

	carry_out<='1'  when Q="1001"	 else '0';	 

	count_BCD_out<="0001"	when (Q=1)	Else
		  	 	"0010"	when (Q=2)	Else
		  	 	"0011"	when (Q=3)	Else
		  	 	"0100"	when (Q=4)	Else
		  	 	"0101"	when (Q=5)	Else
		  	 	"0110"	when (Q=6)	Else
		  	 	"0111"	when (Q=7)	Else
		  	 	"1000"	when (Q=8)	Else
		  	 	"1001"	when (Q=9)	Else
				"0000";

end Behavioral;