top.twr

来自「本代码介绍了使用VHDL开发FPGA的一般流程」· TWR 代码 · 共 176 行

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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml top top.ncd -o top.twr
top.pcf


Design file:              top.ncd
Physical constraint file: top.pcf
Device,speed:             xc2s100,-6 (PRODUCTION 1.27 2003-12-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock RST to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
LED1_SEG<0> |   26.085(F)|LOAD              |   0.000|
LED1_SEG<1> |   26.045(F)|LOAD              |   0.000|
LED1_SEG<2> |   26.021(F)|LOAD              |   0.000|
LED1_SEG<3> |   25.931(F)|LOAD              |   0.000|
LED1_SEG<4> |   26.468(F)|LOAD              |   0.000|
LED1_SEG<5> |   25.442(F)|LOAD              |   0.000|
LED1_SEG<6> |   25.733(F)|LOAD              |   0.000|
LED2_SEG<0> |   24.950(F)|LOAD              |   0.000|
LED2_SEG<1> |   25.165(F)|LOAD              |   0.000|
LED2_SEG<2> |   24.798(F)|LOAD              |   0.000|
LED2_SEG<3> |   24.786(F)|LOAD              |   0.000|
LED2_SEG<4> |   24.816(F)|LOAD              |   0.000|
LED2_SEG<5> |   24.893(F)|LOAD              |   0.000|
LED2_SEG<6> |   24.907(F)|LOAD              |   0.000|
LED3_SEG<0> |   25.327(F)|LOAD              |   0.000|
LED3_SEG<1> |   24.770(F)|LOAD              |   0.000|
LED3_SEG<2> |   24.670(F)|LOAD              |   0.000|
LED3_SEG<3> |   24.805(F)|LOAD              |   0.000|
LED3_SEG<4> |   24.847(F)|LOAD              |   0.000|
LED3_SEG<5> |   24.677(F)|LOAD              |   0.000|
LED3_SEG<6> |   25.222(F)|LOAD              |   0.000|
LED4_SEG<0> |   25.855(F)|LOAD              |   0.000|
LED4_SEG<1> |   25.657(F)|LOAD              |   0.000|
LED4_SEG<2> |   25.681(F)|LOAD              |   0.000|
LED4_SEG<3> |   26.080(F)|LOAD              |   0.000|
LED4_SEG<4> |   26.137(F)|LOAD              |   0.000|
LED4_SEG<5> |   25.557(F)|LOAD              |   0.000|
LED4_SEG<6> |   25.305(F)|LOAD              |   0.000|
LED5_SEG<0> |   25.310(F)|LOAD              |   0.000|
LED5_SEG<1> |   25.058(F)|LOAD              |   0.000|
LED5_SEG<2> |   25.346(F)|LOAD              |   0.000|
LED5_SEG<3> |   25.491(F)|LOAD              |   0.000|
LED5_SEG<4> |   25.838(F)|LOAD              |   0.000|
LED5_SEG<5> |   24.138(F)|LOAD              |   0.000|
LED5_SEG<6> |   24.538(F)|LOAD              |   0.000|
LED6_SEG<0> |   25.766(F)|LOAD              |   0.000|
LED6_SEG<1> |   26.561(F)|LOAD              |   0.000|
LED6_SEG<2> |   25.964(F)|LOAD              |   0.000|
LED6_SEG<3> |   27.059(F)|LOAD              |   0.000|
LED6_SEG<4> |   26.020(F)|LOAD              |   0.000|
LED6_SEG<5> |   25.796(F)|LOAD              |   0.000|
LED6_SEG<6> |   26.507(F)|LOAD              |   0.000|
OVER        |   10.839(F)|LOAD              |   0.000|
------------+------------+------------------+--------+

Clock Switch<0> to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
LED_gate    |   11.595(R)|U1_clk            |   0.000|
------------+------------+------------------+--------+

Clock Switch<1> to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
LED_gate    |   12.078(R)|U1_clk            |   0.000|
------------+------------+------------------+--------+

Clock Switch<2> to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
LED_gate    |   11.988(R)|U1_clk            |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK            |         |         |         |    5.508|
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock CLK_Basic
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK_Basic      |    5.802|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock RST
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK            |         |         |         |    5.457|
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock Switch<0>
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Switch<0>      |    6.389|         |         |    2.582|
Switch<1>      |    6.872|         |         |    3.065|
Switch<2>      |    6.782|         |         |    2.975|
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock Switch<1>
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Switch<0>      |    5.935|         |         |    2.582|
Switch<1>      |    6.418|         |         |    2.611|
Switch<2>      |    6.328|         |         |    2.582|
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock Switch<2>
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Switch<0>      |    6.265|         |         |    2.582|
Switch<1>      |    6.748|         |         |    2.941|
Switch<2>      |    6.658|         |         |    2.851|
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
Switch<0>      |LED_point<0>   |   12.016|
Switch<0>      |LED_point<1>   |   12.065|
Switch<0>      |LED_point<2>   |   11.933|
Switch<1>      |LED_point<0>   |   12.158|
Switch<1>      |LED_point<1>   |   12.138|
Switch<1>      |LED_point<2>   |   12.067|
Switch<2>      |LED_point<0>   |   12.006|
Switch<2>      |LED_point<1>   |   12.187|
Switch<2>      |LED_point<2>   |   11.903|
---------------+---------------+---------+

Analysis completed Mon Dec 18 22:40:47 2006
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Peak Memory Usage: 48 MB