gate.vhdl

来自「本代码介绍了使用VHDL开发FPGA的一般流程」· VHDL 代码 · 共 28 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity GATE is
	PORT(
		CLK,gate0		:IN STD_LOGIC;
		CP		  	:OUT STD_LOGIC
	);
end GATE;

architecture Behavioral of GATE is
begin


 process(CLK,gate0)
 begin
  	CP<=CLK and gate0; 
 end process;

end Behavioral;