top_top_test_vhd_tb.fdo

本代码介绍了使用VHDL开发FPGA的一般流程

## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Mon Dec 18 22:41:02 中国标准时间 2006
##
vlib work
vcom -93 -explicit  free_change.vhdl
vcom -93 -explicit  freq_change.vhdl
vcom -93 -explicit  control_unite.vhdl
vcom -93 -explicit  gate.vhdl
vcom -93 -explicit  counter10.vhdl
vcom -93 -explicit  counter.vhdl
vcom -93 -explicit  data_lock.vhdl
vcom -93 -explicit  bcd2seg_display.vhdl
vcom -93 -explicit  Top.vhdl
vcom -93 -explicit  top_test.vhd
vsim -t 1ps   -lib work top_top_test_vhd_tb
do top_top_test_vhd_tb.udo
view wave
add wave *
view structure
view signals
run 1000ns