data_lock.vhdl

来自「本代码介绍了使用VHDL开发FPGA的一般流程」· VHDL 代码 · 共 37 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Data_Lock is
	PORT(
		OVER_in,LOAD						:IN STD_LOGIC;
		F,E,D,C,B,A 						:IN STD_LOGIC_VECTOR(3 downto 0);
		OVER								:OUT STD_LOGIC;
		BCD_6,BCD_5,BCD_4,BCD_3,BCD_2,BCD_1	:OUT STD_LOGIC_VECTOR(3 downto 0)
	);
end Data_Lock;

architecture Behavioral of Data_Lock is

begin
Process(LOAD)
	begin
	if LOAD='1' 	then
			BCD_6<=F;
			BCD_5<=E;
			BCD_4<=D;
			BCD_3<=C;
			BCD_2<=B;
			BCD_1<=A;
			OVER<=OVER_in;
	end if;
end process;

end Behavioral;