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本代码介绍了使用VHDL开发FPGA的一般流程

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "CLK"  LOC = "p80"  ;
NET "CLK_Basic"  LOC = "p182"  ;
NET "LED1_SEG<0>"  LOC = "p109"  ;
NET "LED1_SEG<1>"  LOC = "p110"  ;
NET "LED1_SEG<2>"  LOC = "p101"  ;
NET "LED1_SEG<3>"  LOC = "p102"  ;
NET "LED1_SEG<4>"  LOC = "p108"  ;
NET "LED1_SEG<5>"  LOC = "p112"  ;
NET "LED1_SEG<6>"  LOC = "p111"  ;
NET "LED2_SEG<0>"  LOC = "p90"  ;
NET "LED2_SEG<1>"  LOC = "p94"  ;
NET "LED2_SEG<2>"  LOC = "p84"  ;
NET "LED2_SEG<3>"  LOC = "p86"  ;
NET "LED2_SEG<4>"  LOC = "p88"  ;
NET "LED2_SEG<5>"  LOC = "p96"  ;
NET "LED2_SEG<6>"  LOC = "p95"  ;
NET "LED3_SEG<0>"  LOC = "p74"  ;
NET "LED3_SEG<1>"  LOC = "p75"  ;
NET "LED3_SEG<2>"  LOC = "p70"  ;
NET "LED3_SEG<3>"  LOC = "p71"  ;
NET "LED3_SEG<4>"  LOC = "p73"  ;
NET "LED3_SEG<5>"  LOC = "p82"  ;
NET "LED3_SEG<6>"  LOC = "p81"  ;
NET "LED4_SEG<0>"  LOC = "p62"  ;
NET "LED4_SEG<1>"  LOC = "p63"  ;
NET "LED4_SEG<2>"  LOC = "p69"  ;
NET "LED4_SEG<3>"  LOC = "p58"  ;
NET "LED4_SEG<4>"  LOC = "p60"  ;
NET "LED4_SEG<5>"  LOC = "p68"  ;
NET "LED4_SEG<6>"  LOC = "p67"  ;
NET "LED5_SEG<0>"  LOC = "p97"  ;
NET "LED5_SEG<1>"  LOC = "p89"  ;
NET "LED5_SEG<2>"  LOC = "p100"  ;
NET "LED5_SEG<3>"  LOC = "p99"  ;
NET "LED5_SEG<4>"  LOC = "p98"  ;
NET "LED5_SEG<5>"  LOC = "p83"  ;
NET "LED5_SEG<6>"  LOC = "p87"  ;
NET "LED6_SEG<0>"  LOC = "p49"  ;
NET "LED6_SEG<1>"  LOC = "p57"  ;
NET "LED6_SEG<2>"  LOC = "p46"  ;
NET "LED6_SEG<3>"  LOC = "p47"  ;
NET "LED6_SEG<4>"  LOC = "p48"  ;
NET "LED6_SEG<5>"  LOC = "p61"  ;
NET "LED6_SEG<6>"  LOC = "p59"  ;
NET "LED_gate"  LOC = "p132"  ;
NET "LED_point<0>"  LOC = "p120"  ;
NET "LED_point<1>"  LOC = "p115"  ;
NET "LED_point<2>"  LOC = "p113"  ;
NET "OVER"  LOC = "p134"  ;
NET "RST"  LOC = "p193"  ;
NET "Switch<0>"  LOC = "p5"  ;
NET "Switch<1>"  LOC = "p4"  ;
NET "Switch<2>"  LOC = "p3"  ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE