freqtest.vhd

四位十进制频率计的源代码,详细,清楚地写出了设计语句

LIBRARY IEEE;
LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FREQTEST IS
    PORT ( CLK1HZ : IN STD_LOGIC;    
             FSIN : IN STD_LOGIC;
                LK: IN STD_LOGIC;
                LM:OUT BIT;
              --DOUT1, DOUT2, DOUT3, DOUT4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
              SG  : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
              BT  : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));  
    END FREQTEST;
   ARCHITECTURE struc OF FREQTEST IS
COMPONENT FTCTRL
    PORT (CLKK : IN STD_LOGIC;                 
        CNT_EN : OUT STD_LOGIC;                 
       RST_CNT : OUT STD_LOGIC;               
         Load : OUT STD_LOGIC   );                  
 END COMPONENT;
COMPONENT COUNTER
   PORT (FIN : IN STD_LOGIC;                      
          CLR : IN STD_LOGIC;                           
        ENABL : IN STD_LOGIC;                        
        DOUT1,DOUT2,DOUT3,DOUT4 :  OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); 
END COMPONENT; 
COMPONENT REG24B
   PORT ( LK : IN STD_LOGIC;
       DIN1,DIN2,DIN3,DIN4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      DOUT1, DOUT2, DOUT3, DOUT4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
END COMPONENT;
SIGNAL TSTEN1 : STD_LOGIC;
    SIGNAL CLR_CNT1 : STD_LOGIC;
    SIGNAL Load1 : STD_LOGIC;
    SIGNAL DTO1,DTO2,DTO3,DTO4 : STD_LOGIC_VECTOR(3 DOWNTO 0);
    --SIGNAL CARRY_OUT1 : STD_LOGIC_VECTOR(6 DOWNTO 0);
    SIGNAL DOUT1,DOUT2,DOUT3,DOUT4:STD_LOGIC_VECTOR(3 DOWNTO 0);
    SIGNAL CNT8 : STD_LOGIC_VECTOR(2 DOWNTO 0);
    SIGNAL   A : INTEGER RANGE 0 TO 10;
BEGIN 
LM<='0';
  u1:  FTCTRL PORT MAP(CLKK =>CLK1HZ,CNT_EN=>TSTEN1,
  RST_CNT =>CLR_CNT1,Load =>Load1);
  u2:  REG24B PORT MAP( LK =>Load1,DIN1 =>DTO1,DIN2 =>DTO2,DIN3 =>DTO3,DIN4 =>DTO4,DOUT1=>DOUT1,DOUT2=>DOUT2,DOUT3=>DOUT3,DOUT4=>DOUT4);
  u3:COUNTER PORT MAP( FIN => FSIN,CLR =>CLR_CNT1,ENABL =>TSTEN1,DOUT1=>DTO1,
DOUT2=>DTO2,DOUT3=>DTO3,DOUT4=>DTO4);
P1:PROCESS( CNT8 )
    BEGIN
        CASE  CNT8  IS
          WHEN "000" =>  BT <= CNT8;
                                 A <=  CONV_INTEGER(DOUT1(3  DOWNTO 0 ));
          WHEN "001" =>  BT <= CNT8 ; 
                                 A <=  CONV_INTEGER(DOUT2(3  DOWNTO 0 )); 
          WHEN "010" =>  BT <= CNT8 ; 
                                 A <=  CONV_INTEGER(DOUT3(3  DOWNTO 0 ));
          WHEN "011" =>  BT <= CNT8 ; 
                                A <= CONV_INTEGER(DOUT4(3  DOWNTO 0 ));
                        WHEN OTHERS =>  NULL ;

        END CASE;
     END PROCESS P1;
P2:PROCESS(CLK1HZ)
        BEGIN
         IF CLK1HZ'EVENT AND CLK1HZ = '1' THEN
       if cnt8<5  then  CNT8 <= CNT8 + 1;  
else cnt8 <=(OTHERS=>'0'); 


         END IF;
         END IF;
       
	   END PROCESS P2 ;
P3:PROCESS( A ) 
        BEGIN
       CASE  A  IS
        WHEN 0  => SG <= "0111111";  WHEN 1  => SG <= "0000110"; 
        WHEN 2  => SG <= "1011011";  WHEN 3  => SG <= "1001111"; 
        WHEN 4  => SG <= "1100110";  WHEN 5  => SG <= "1101101"; 
        WHEN 6  => SG <= "1111101";  WHEN 7  => SG <= "0000111";
        WHEN 8  => SG <= "1111111";  WHEN 9  => SG <= "1101111"; 
        WHEN 10 => SG <= "1110111";          
       WHEN OTHERS =>  NULL ;
       END CASE ;
      END PROCESS P3;  
END struc;