reg24b.vhd

来自「四位十进制频率计的源代码,详细,清楚地写出了设计语句」· VHDL 代码 · 共 17 行

LIBRARY IEEE;  
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG24B IS
 PORT ( LK : IN STD_LOGIC;
       DIN1,DIN2,DIN3,DIN4 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
      DOUT1, DOUT2, DOUT3, DOUT4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );
END REG24B;
ARCHITECTURE behav OF REG24B IS
BEGIN
    PROCESS(LK, DIN1,DIN2,DIN3,DIN4)
   BEGIN
   IF LK'EVENT AND LK = '1' THEN  DOUT1 <= DIN1; DOUT2 <= DIN2; DOUT3 <= DIN3;  DOUT4 <= DIN4; 
        END IF;
    END PROCESS;
END behav;