ftctrl.vhd

来自「四位十进制频率计的源代码,详细,清楚地写出了设计语句」· VHDL 代码 · 共 27 行

LIBRARY IEEE;  
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY  FTCTRL  IS
    PORT (CLKK : IN STD_LOGIC;                        
 CNT_EN : OUT STD_LOGIC;                 
       RST_CNT : OUT STD_LOGIC;                 
         Load : OUT STD_LOGIC    );  
end ftctrl;
ARCHITECTURE  behav  OF  FTCTRL IS
    SIGNAL Div2CLK : STD_LOGIC;
BEGIN
    PROCESS( CLKK )
    BEGIN
IF CLKK'EVENT AND CLKK = '1' THEN   
      Div2CLK <= NOT Div2CLK;           
        END IF;
    END PROCESS;
PROCESS (CLKK, Div2CLK)
    BEGIN
        IF CLKK='0' AND Div2CLK='0' THEN RST_CNT<='1';  
          ELSE RST_CNT <= '0';  END IF;
    END PROCESS;
    Load  <= NOT Div2CLK;    CNT_EN <= Div2CLK;
END behav;