📄 counter.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNTER IS
PORT (FIN : IN STD_LOGIC;
CLR : IN STD_LOGIC;
ENABL : IN STD_LOGIC;
DOUT1,DOUT2,DOUT3,DOUT4 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COUNTER;
ARCHITECTURE behav OF COUNTER IS
SIGNAL c1:STD_LOGIC;
SIGNAL c2:STD_LOGIC;
SIGNAL c3:STD_LOGIC;
SIGNAL c4:STD_LOGIC;
BEGIN
a:PROCESS(FIN, CLR, ENABL)
variable w1:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF CLR = '1' THEN w1 :=(OTHERS=>'0');
ELSIF FIN'EVENT AND FIN = '1' THEN
IF ENABL = '1' THEN
if w1<9 then w1 :=w1+ 1;
else w1 :=(OTHERS=>'0');
END IF;
END IF;
END IF;
if w1=9 then c1<='1';
else c1<='0';
end if;
DOUT1(3 DOWNTO 0)<=w1(3 DOWNTO 0 );
END PROCESS a;
b:PROCESS(c1, clr, ENABL)
variable w2:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF CLR = '1' THEN w2:=(OTHERS=>'0');
ELSIF c1'EVENT AND c1 = '0' THEN
IF ENABL = '1' THEN
if w2<9 then w2 := w2 + 1;
else w2:=(OTHERS=>'0');
END IF;
END IF;
END IF;
if w2=9 then c2<='1';
else c2<='0';
end if;
DOUT2(3 DOWNTO 0)<=w2(3 DOWNTO 0);
END PROCESS b;
c:PROCESS(c2, clr, ENABL)
variable w3:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF CLR = '1' THEN w3:=(OTHERS=>'0');
ELSIF c2'EVENT AND c2 = '0' THEN
IF ENABL = '1' THEN
if w3<9 then w3 := w3 + 1;
else w3:=(others=>'0');
END IF;
END IF;
END IF;
if w3=9 then c3<='1';
else c3<='0';
end if;
DOUT3(3 DOWNTO 0)<=w3(3 DOWNTO 0 );
END PROCESS c;
d:PROCESS(c3, clr, ENABL)
variable w4:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF CLR = '1' THEN w4:= (OTHERS=>'0');
ELSIF c3'EVENT AND c3 = '0' THEN
IF ENABL = '1' THEN
if w4<9 then w4 := w4 + 1;
else w4:=(others=>'0');
END IF;
END IF;
END IF;
if w4=9 then c4<='1';
else c4<='0';
end if;
DOUT4(3 DOWNTO 0)<=w4(3 DOWNTO 0 );
END PROCESS d;
END behav;
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