sine_fshift.vhd

来自「三相直接数字频率合成器dds的VHDL源码」· VHDL 代码 · 共 54 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rom_constants.all;

ENTITY sine_Fshift IS
	PORT(
		dataa	: IN STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0);
		datab	: IN STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0);
		result	: OUT STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0));
END sine_Fshift;

ARCHITECTURE a OF sine_Fshift IS
	SIGNAL temp1,temp2: STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0);
    SIGNAL s: STD_LOGIC;

    COMPONENT sine_add
      	PORT(
		    dataa	: IN STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0);
		    datab	: IN STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0);
		    result	: OUT STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0));
    END COMPONENT;
    
    COMPONENT sine_sub
      	PORT(
		    dataa	: IN STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0);
		    result	: OUT STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0));
    END COMPONENT;
    
    COMPONENT sine_compare
      	PORT(
		    dataa : IN STD_LOGIC_VECTOR (ADDR_WIDTH-1 DOWNTO 0);
		    AeB	  : OUT STD_LOGIC ;
		    AgeB  : OUT STD_LOGIC );
    END COMPONENT;

    
BEGIN
	P_sine_add: sine_add
    PORT MAP (dataa=>dataa, datab=> datab,  result=>temp1);

    P_sine_sub: sine_sub
    PORT MAP (dataa=>temp1,  result=>temp2);
    
    P_sine_compare:sine_compare
    PORT MAP (dataa=>temp1,  AgeB=>s);

    result<=temp1 when s='0' else
            temp2; 
END a;