sine3.vhd

三相直接数字频率合成器dds的VHDL源码

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
--LIBRARY work;
--USE work.ram_constants.ALL;


ENTITY sine3 IS
	GENERIC(ROM_LONTH : integer:=  120;
            ADDR_LONTH: integer:=  8;
            XIANG_YI  : integer:=  120;
	        DATA_LENTH: integer:=  8);
	PORT(
		 clk		: IN	STD_LOGIC;  --cai yang pin lv 5 bei
         rest		: IN	STD_LOGIC;
		sineA, sineB,sineC: OUT	STD_LOGIC_VECTOR(DATA_LENTH downto 0));
END sine3;
ARCHITECTURE a OF sine3 IS
	SIGNAL sineA_latcd,sineB_latch,sineC_latch:STD_LOGIC_VECTOR(DATA_LENTH downto 0);
	SIGNAL sineA_temp,sineB_temp,sineC_temp   :STD_LOGIC_VECTOR(DATA_LENTH downto 0);
    SIGNAL temp ,addr,addrA,addrB,addrC       :STD_LOGIC_VECTOR(ADDR_LONTH downto 0);
    SIGNAL state      :STD_LOGIC_VECTOR(2 downto 0);
BEGIN
	state_control:
	PROCESS (clk, rest)
	BEGIN
		IF rest='1'THEN
		    state<="000";
		ELSIF (clk'event and clk='1')THEN
		    if state<"101"then
		       state<=state+1;
            else
               state<="000";
            end if;
		END IF;
	END PROCESS state_control;
	
	state_exe:
	PROCESS (clk,rest)
	BEGIN
        if(rest='1')then
            addrA<= others<='0';
        elsif(clk'event and clk='0')THEN

		    CASE state IS
			    WHEN "000"=>
			       addrA<=addrA+1;
			       addrB<=addrA+XIANG_YI;
                   addrC<=addrB+XIANG_YI;
			    WHEN "001"=>
			        addr<=addrA;
			        sineA_temp<=data;
                WHEN "010"=>
			        addr<=addrB;
			        sineB_temp<=data;
                WHEN "011"=>
			        addr<=addrC;
			        sineC_temp<=data;
                WHEN "100"=>
			        sineA_latch<=sineA_temp<=data;
                    sineB_latch<=sineB_temp<=data;
			        sineC_latch<=sineC_temp<=data;
			    WHEN OTHERS =>
			        addrA<= others<='0';
		        END CASE;
        end if;
	END PROCESS state_exe;
	    

	--  Generate Statement
END a;