sine_latch.vhd

来自「三相直接数字频率合成器dds的VHDL源码」· VHDL 代码 · 共 34 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.rom_constants.all;

ENTITY sine_latch IS
	PORT(
		ale    : IN	STD_LOGIC; --ale up lock
        reset  : IN	STD_LOGIC; 
        clr    : IN	STD_LOGIC;
		datain     : IN	STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
		dataout   : OUT	STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0));
END sine_latch;
ARCHITECTURE a OF sine_latch IS
    SIGNAL temp: STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
    
BEGIN
	
	PROCESS (ale, reset,clr)
	BEGIN
		IF(reset='1'or clr='1')THEN
            temp<= (others =>'0');
        ELSIF(ale'EVENT AND ale= '1') THEN
            temp<=datain;         
		END IF;
	END PROCESS;

    dataout<=temp;
END a;