sine_state.vhd

三相直接数字频率合成器dds的VHDL源码

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY sine_state IS
PORT(
        reset      : IN	STD_LOGIC;
		clock      : IN	STD_LOGIC;
        One_T      : IN	STD_LOGIC;  --1 san xiang  0 yixiang
        clock_add  : OUT STD_LOGIC;
		sel_ad     : OUT STD_LOGIC_VECTOR(1 downto 0);
        sel_da     : OUT STD_LOGIC_VECTOR(1 downto 0);
        ale_latch1 : OUT STD_LOGIC_VECTOR(3 downto 0);
		ale_latch2 : OUT STD_LOGIC;
		clr_latch1 : OUT STD_LOGIC_VECTOR(3 downto 0)
        );
END sine_state;

ARCHITECTURE a OF sine_state IS
	TYPE state IS ( idle, phadd,wait0, openA, lockA, openB, lockB, openC, lockC,lockOUT);
	SIGNAL cur_state, nex_state :state;
BEGIN

update_state :	-- Update the state on the clock edge
PROCESS (reset, clock)
BEGIN
   IF (reset='1') THEN
	  cur_state <= idle ;
   ELSIF clock'event and clock='1' THEN
	  cur_state <= nex_state ;
   END IF ;
END PROCESS;

transitions :	-- set the outputs and next state
PROCESS (cur_state,One_T,clock)
BEGIN
   if clock'event and clock='0' then  --利用时钟来减少毛刺
      CASE cur_state IS
	    WHEN idle =>
            clock_add<='0';
		    sel_ad<="11";
            sel_da<="11";  
            ale_latch1<="0000";
		    ale_latch2<='0';
		    clr_latch1<="0000";
            nex_state<=phadd;
	    WHEN phadd =>       
	        clock_add<='1';
            ale_latch2<='0';
            nex_state<=wait0;
	    WHEN wait0 => 
            clock_add<='0';      
	        nex_state<=openA;
	    WHEN openA =>      
            sel_ad<="00";
            sel_da<="00"; 
            nex_state<=lockA;
	    WHEN lockA =>       
	        ale_latch1<="0001";
	        nex_state<=openB;
	    WHEN openB =>       
	        ale_latch1<="0000";
            if One_T='1' then
               sel_ad<="01";
               sel_da<="01";
            end if;
 
            nex_state<=lockB;
	    WHEN lockB =>
            if One_T='0' then
               clr_latch1<="0010";
            else
               ale_latch1<="0010";
            end if;
	        nex_state<=openC;
	    WHEN openC => 
            clr_latch1<="0000";      
	        ale_latch1<="0000";           
            if One_T='1' then
               sel_ad<="10";
               sel_da<="10";
            end if;
            nex_state<=lockC;
	    WHEN lockC =>
            if One_T='0' then
               clr_latch1<="0100";
            else
               ale_latch1<="0100";
            end if;
   	        nex_state<=lockOUT;
	    WHEN lockOUT =>
            clr_latch1<="0000";       
	        ale_latch2<='1';
            nex_state<=idle;
        WHEN OTHERS =>
            nex_state<=idle;
	END CASE;
  end if;
END PROCESS;
END a;