phase_acc.vhd

来自「三相直接数字频率合成器dds的VHDL源码」· VHDL 代码 · 共 37 行

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
USE work.rom_constants.all;

ENTITY phase_acc IS
	PORT(
		clock	: IN	STD_LOGIC;
		reset   : IN	STD_LOGIC;
		cnt		: OUT	STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0)
        );
END phase_acc;
ARCHITECTURE a OF phase_acc IS
	SIGNAL counter : STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
BEGIN
	coutter_p:
	PROCESS (clock, reset)
	BEGIN
		IF reset='1' THEN
		    counter<=(others =>'0');
		ELSIF clock'event and clock='1' THEN
		    IF counter=359 THEN
                counter<=(others =>'0');
            ELSE
                counter<= counter+1;
            END IF;
		END IF;
	END PROCESS coutter_p;

    cnt<=counter;
END a;