sine_1to4.vhd

来自「三相直接数字频率合成器dds的VHDL源码」· VHDL 代码 · 共 40 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.rom_constants.all;

ENTITY sine_1to4 IS
	PORT(
		sel	    :IN	STD_LOGIC_VECTOR(1 downto 0);
        in_data :IN STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
		out_a   :OUT	STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        out_b   :OUT	STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        out_c   :OUT	STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0);
        out_d   :OUT	STD_LOGIC_VECTOR(DATA_WIDTH-1 downto 0)
		);
	
END sine_1to4;

ARCHITECTURE a OF sine_1to4 IS
	
BEGIN
  process(sel) 
  begin
     CASE sel IS
     	WHEN "00"=>
     	    out_a<=in_data;
     	WHEN "01"=>
     	    out_b<=in_data;
        WHEN "10"=>
     	    out_c<=in_data;
        WHEN "11"=>
     	    out_d<=in_data;
     	WHEN OTHERS =>
     	    out_a<= (others=>'X');
            out_b<= (others=>'X');
            out_c<= (others=>'X');
            out_d<= (others=>'X');
     END CASE;		
  end process;
END a;