sine_div.vhd

三相直接数字频率合成器dds的VHDL源码

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY sine_div IS
	PORT(
		clk		: IN	STD_LOGIC;
		reset   : IN	STD_LOGIC;
		clock   : OUT	STD_LOGIC);
END sine_div;

ARCHITECTURE a OF sine_div IS
BEGIN
	PROCESS (reset, clk)
         VARIABLE counter : STD_LOGIC_VECTOR(7 downto 0);
         
	BEGIN
		IF reset='1' THEN
		    counter:=(others => '0');
		ELSIF clk'event and clk='1' THEN
   		    counter:=counter+1;	
            IF counter=66 THEN
		        clock<='1';
		    ELSIF counter=133 THEN
		        clock<='1';
            ELSIF counter=200 THEN
		        clock<='1';	
                counter:=(others => '0');
            ELSE
		        clock<='0';
		    END IF;
    		    
		END IF;
    END PROCESS ;
END a;