sine_4to1.vhd

来自「三相直接数字频率合成器dds的VHDL源码」· VHDL 代码 · 共 37 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.rom_constants.all;

ENTITY sine_4to1 IS
	PORT(
		sel	:IN	STD_LOGIC_VECTOR(1 downto 0);
		in_a:IN	STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
        in_b:IN	STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
        in_c:IN	STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
       -- in_d:IN	STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0);
		q   :OUT STD_LOGIC_VECTOR(ADDR_WIDTH-1 downto 0)
        );
	
END sine_4to1;

ARCHITECTURE a OF sine_4to1 IS
	
BEGIN
  process(sel) 
  begin
     CASE sel IS
     	WHEN "00"=>
     	    q<=in_a;
     	WHEN "01"=>
     	    q<=in_b;
        WHEN "10"=>
     	    q<=in_c;
        --WHEN "11"=>
     	    --q<=in_d;
     	WHEN OTHERS =>
     	    q<= (others=>'0');
     END CASE;		
  end process;
END a;