📄 txd5.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity txd5 is
port(indata:in std_logic_vector(7 downto 0);
cs,wr,clock:in std_logic;
txd,ti:out std_logic);
end txd5;
architecture behave of txd5 is
signal sig_count:std_logic_vector(3 downto 0);
signal sig_ti,sig_txd,sig_buffer,sig_mark:std_logic;
signal sig_txddata:std_logic_vector(9 downto 0);
begin
process (clock)
begin
if(clock'event and clock='1')then
if(cs='0')then
if(sig_buffer='0')then
if(wr='1')then
for i in 8 downto 1 loop
sig_txddata(i)<=indata(i-1);
if(i=8)then
sig_mark<=sig_txddata(i);
else
sig_mark<=sig_mark xor sig_txddata(i);
end if;
end loop;
sig_txddata(9)<='0';
if(sig_mark='0')then
sig_txddata(0)<='0';
else
sig_txddata(0)<='1';
end if;
sig_buffer<='1';
end if;
else
sig_txd<=sig_txddata(9);
for i in 9 downto 1 loop
sig_txddata(i)<=sig_txddata(i-1);
end loop;
sig_txddata(0)<='1';
if(sig_count="1011")then
sig_count<="0000";
sig_ti<='0';
elsif(sig_count="0000" and sig_ti='0')then
sig_buffer<='0';
sig_ti<='1';
else
sig_count<=sig_count+'1';
sig_ti<='1';
end if;
end if;
end if;
end if;
end process;
process
begin
if(sig_ti='0')then
txd<='1';
else txd<=sig_txd;
end if;
end process;
ti<= sig_ti;
end behave;
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