system1.sim.qmsg

来自「用VHDL语言实现的控制DS18B20构成测温仪表的程序」· QMSG 代码 · 共 79 行 · 第 1/3 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 27 10:39:20 2006 " "Info: Processing started: Fri Oct 27 10:39:20 2006" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off system1 -c system1 " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off system1 -c system1" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|system1\|led_convertor:display_component\|state_6 " "Warning: Can't display state machine states -- register holding state machine bit \"\|system1\|led_convertor:display_component\|state_6\" was synthesized away" {  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 87 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|system1\|led_convertor:display_component\|state_4 " "Warning: Can't display state machine states -- register holding state machine bit \"\|system1\|led_convertor:display_component\|state_4\" was synthesized away" {  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 87 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0}
{ "Warning" "WSIM_MACHINE_BIT_NOT_FOUND" "\|system1\|led_convertor:display_component\|state_1 " "Warning: Can't display state machine states -- register holding state machine bit \"\|system1\|led_convertor:display_component\|state_1\" was synthesized away" {  } { { "led_convertor.vhd" "" { Text "D:/altera/my vhdl file/system1/led_convertor.vhd" 87 -1 0 } }  } 0 0 "Can't display state machine states -- register holding state machine bit \"%1!s!\" was synthesized away" 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "closedot\[7\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"closedot\[7\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "closedot\[7\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "closedot\[6\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"closedot\[6\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "closedot\[6\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "closedot\[5\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"closedot\[5\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "closedot\[5\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "closedot\[4\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"closedot\[4\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "closedot\[4\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "closedot\[3\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"closedot\[3\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "closedot\[3\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "closedot\[2\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"closedot\[2\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "closedot\[2\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "closedot\[1\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"closedot\[1\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "closedot\[1\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "closedot\[0\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"closedot\[0\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "closedot\[0\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "gate " "Warning: Ignored node in vector source file. Can't find corresponding node name \"gate\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "gate" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[72\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[72\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[72\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[71\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[71\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[71\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[70\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[70\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[70\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[69\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[69\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[69\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[68\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[68\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[68\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[67\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[67\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[67\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[66\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[66\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[66\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[65\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[65\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[65\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[64\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[64\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[64\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[63\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[63\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[63\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[62\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[62\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[62\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[61\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[61\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[61\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}