system1.sim.qmsg

来自「用VHDL语言实现的控制DS18B20构成测温仪表的程序」· QMSG 代码 · 共 79 行 · 第 1/3 页

{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[33\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[33\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[33\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[32\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[32\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[32\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[31\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[31\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[31\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[30\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[30\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[30\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[29\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[29\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[29\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[28\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[28\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[28\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[27\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[27\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[27\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[26\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[26\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[26\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[25\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[25\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[25\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[24\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[24\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[24\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[23\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[23\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[23\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[22\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[22\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[22\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[21\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[21\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[21\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[20\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[20\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[20\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[19\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[19\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[19\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[18\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[18\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[18\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[17\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[17\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[17\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[16\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[16\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[16\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[15\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[15\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[15\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[14\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[14\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[14\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[13\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[13\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[13\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "ramdata\[12\] " "Warning: Ignored node in vector source file. Can't find corresponding node name \"ramdata\[12\]\" in design." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "ramdata\[12\]" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_WRONG_CHANNEL_FOUND" "\|system1\|allstate Enum 1 9-Level 1 " "Warning: Wrong node type and/or width for node \"\|system1\|allstate\" in vector source file. Node in design is of type Enum and of width 1, but node in vector source file is of type 9-Level and of width 1." {  } { { "D:/altera/my vhdl file/system1/system1.vwf" "" { Waveform "D:/altera/my vhdl file/system1/system1.vwf" "\|system1\|allstate" "0 ps" "0 ps" "" } } { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 24 -1 0 } }  } 0 0 "Wrong node type and/or width for node \"%1!s!\" in vector source file. Node in design is of type %2!s! and of width %3!d!, but node in vector source file is of type %4!s! and of width %5!d!." 0 0}
{ "Warning" "WSIM_CHANNEL_CHANGED_TO_ENUM" "\|system1\|allstate " "Warning: Signal name \"\|system1\|allstate\" changed to enum type" {  } { { "system1.vhd" "" { Text "D:/altera/my vhdl file/system1/system1.vhd" 24 -1 0 } }  } 0 0 "Signal name \"%1!s!\" changed to enum type" 0 0}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0}  } {  } 0 0 "Option to preserve fewer signal transitions to reduce memory r