display.vhd

一个有效位为4位的十进制的数字频率计,VHDL语言编写

--
--  File: display.vhd
--  数码管动态显示译码电路
--  输入：1KHZ时钟，两个数，
--  输出：位选col，数据led

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity display is
	port ( 	
		data1: in INTEGER range 0 to 9;
		data2: in INTEGER range 0 to 9;
		data3: in INTEGER range 0 to 9;
		data4: in INTEGER range 0 to 9;
		overflow:in STD_LOGIC;
		led1: out STD_LOGIC_VECTOR(3 downto 0);
		led2: out STD_LOGIC_VECTOR(3 downto 0);
		led3: out STD_LOGIC_VECTOR(3 downto 0);
		led4: out STD_LOGIC_VECTOR(3 downto 0)		
	);
end display;


architecture rtl of display is
begin  
	process(data1,data2,data3,data4,overflow)
	begin
		if(overflow='1') then
			led1<="1111";led2<="1111";led3<="1111";led4<="1111";
		else
			led1<=CONV_STD_LOGIC_VECTOR(data1,4);
			led2<=CONV_STD_LOGIC_VECTOR(data2,4);
			led3<=CONV_STD_LOGIC_VECTOR(data3,4);
			led4<=CONV_STD_LOGIC_VECTOR(data4,4);
		end if;
	end process;
end rtl;