fdiv.vhd

来自「一个有效位为4位的十进制的数字频率计,VHDL语言编写」· VHDL 代码 · 共 29 行

--
--  File: fdiv10.vhd
-- 	对输入时钟2m分频得

library IEEE;
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;

entity fdiv is  	
	port ( 	    
		clkin: in STD_LOGIC;
		clkout: out STD_LOGIC
	);
end fdiv;

architecture rtl of fdiv is
signal clk:STD_LOGIC;
begin 
	process(clkin)
	begin 
		if rising_edge(clkin) then 				
			clk<=not clk;
		end if;
	end process; 
	
	clkout<=clk;
end rtl;