latcher.vhd

一个有效位为4位的十进制的数字频率计,VHDL语言编写

--
--  File: latcher.vhd
--  下降沿锁存器

library IEEE;
use IEEE.std_logic_1164.all;

entity latcher is
	port (
		clk: in STD_LOGIC;
		d: in INTEGER range 0 to 9;
		q: out INTEGER range 0 to 9
	);
end latcher;


architecture rtl of latcher is
begin  
	process(clk)  
	begin
	if falling_edge(clk) then
		q<=d;
	end if;
	end process;
  
end rtl;