adder4t.v

来自「这是个基于 Xilinx Spartan3 的加法器」· Verilog 代码 · 共 50 行

`timescale  1ns/1ns
module adder4_adder4t_v_tf();

// DATE:     13:16:25 12/18/2005 
// MODULE:   adder4
// DESIGN:   adder4
// FILENAME: adder4t.v
// PROJECT:  adder
// VERSION:  

  
// Inputs			     
    reg [3:0] ina;
    reg [3:0] inb;
    reg cin;


// Outputs
    wire cout;
    wire [3:0] sum;


// Bidirs
    integer i,j;

// Instantiate the UUT
    adder4 adder(cout, sum, ina, inb, cin);

       always  #5 cin=~cin;
       initial begin
            ina = 0;
            inb = 0;
            cin = 0;
		  for (i=1;i<16;i=i+1)
		  #10  ina=i;
        end

	  initial begin
	       for (j=1;j<16;j=j+1)
		  #10  inb=j;
	   end

       initial begin
	   $monitor($time,,,"%d  + %d +%b = {%b,%d}",ina,inb,cin,cout,sum);
	   #160 $finish;
	   end
endmodule