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来自「这是个基于 Xilinx Spartan3 的加法器」· LOG 代码 · 共 661 行 · 第 1/2 页
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Project Navigator Auto-Make Log File-------------------------------------
Started process "View RTL Schematic".=========================================================================* HDL Compilation *=========================================================================Compiling source file "adder4.v"Module <adder4> compiledNo errors in compilationAnalysis of file <adder4.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <adder4>.Module <adder4> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <adder4>. Related source file is adder4.v. Found 4-bit adder carry in/out for signal <$n0000>. Summary: inferred 1 Adder/Subtracter(s).Unit <adder4> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Adders/Subtractors : 1 4-bit adder carry in/out : 1==================================================================================================================================================* Low Level Synthesis *==================================================================================================================================================* Final Report *=========================================================================Completed process "View RTL Schematic".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling source file "adder4.v"tdtfi(verilog) completed successfully.
Release 6.3i - spl2sym G.35Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Compiling source file "adder4.v"tdtfi(verilog) completed successfully.
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling source file "adder4.v"Module <adder4> compiledNo errors in compilationAnalysis of file <adder4.prj> succeeded. =========================================================================* HDL Analysis *=========================================================================Analyzing top module <adder4>.Module <adder4> is correct for synthesis. =========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <adder4>. Related source file is adder4.v. Found 4-bit adder carry in/out for signal <$n0000>. Summary: inferred 1 Adder/Subtracter(s).Unit <adder4> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Adders/Subtractors : 1 4-bit adder carry in/out : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <adder4> ...Loading device for application Xst from file '2s15.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block adder4, actual ratio is 1.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s15cs144-6 Number of Slices: 2 out of 192 1% Number of 4 input LUTs: 4 out of 384 1% Number of bonded IOBs: 14 out of 90 15% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -6 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 9.226ns=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Translate".Command Line: ngdbuild -intstyle ise -dd f:\xilinxlab\myfirst\adder/_ngo -i -pxc2s15-cs144-6 adder4.ngc adder4.ngd Reading NGO file "f:/xilinxlab/myfirst/adder/adder4.ngc" ...Reading component libraries for design expansion...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Total memory usage is 39144 kilobytesWriting NGD file "adder4.ngd" ...Writing NGDBUILD log file "adder4.bld"...NGDBUILD done.Completed process "Translate".
Started process "Map".Using target part "2s15cs144-6".Removing unused or disabled logic...Running cover...Running directed packing...Running delay-based LUT packing...Running related packing...Design Summary:Number of errors: 0Number of warnings: 0Logic Utilization: Number of 4 input LUTs: 4 out of 384 1%Logic Distribution: Number of occupied Slices: 2 out of 192 1% Number of Slices containing only related logic: 2 out of 2 100% Number of Slices containing unrelated logic: 0 out of 2 0% *See NOTES below for an explanation of the effects of unrelated logicTotal Number of 4 input LUTs: 4 out of 384 1% Number of bonded IOBs: 14 out of 86 16%Total equivalent gate count for design: 48Additional JTAG gate count for IOBs: 672Peak Memory Usage: 55 MBNOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design.Mapping completed.See MAP report file "adder4_map.mrp" for details.Completed process "Map".Mapping Module adder4 . . .
MAP command line:
map -intstyle ise -p xc2s15-cs144-6 -cm area -pr b -k 4 -c 100 -tx off -o adder4_map.ncd adder4.ngd adder4.pcf
Mapping Module adder4: DONE
Started process "Place & Route Report".Constraints file: adder4.pcfLoading device database for application Par from file "adder4_map.ncd". "adder4" is an NCD, version 2.38, device xc2s15, package cs144, speed -6Loading device for application Par from file '2s15.nph' in environmentD:/Xilinx.Device speed data version: PRODUCTION 1.27 2004-06-25.Resolving physical constraints.Finished resolving physical constraints.Device utilization summary: Number of External IOBs 14 out of 86 16% Number of LOCed External IOBs 0 out of 14 0% Number of SLICEs 2 out of 192 1%Overall effort level (-ol): Standard (set by user)Placer effort level (-pl): Standard (set by user)Placer cost table entry (-t): 1Router effort level (-rl): Standard (set by user)⌨️ 快捷键说明
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