transcript

这是个基于 Xilinx Spartan3 的加法器

# Reading D:/Modeltech_6.0/tcl/vsim/pref.tcl 
# //  ModelSim SE 6.0 Aug 19 2004 
# //
# //  Copyright Mentor Graphics Corporation 2004
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# do adder4_adder4t_v_tf.fdo 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004
# -- Compiling module adder4
# 
# Top level modules:
# 	adder4
# Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004
# -- Compiling module adder4_adder4t_v_tf
# 
# Top level modules:
# 	adder4_adder4t_v_tf
# Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004
# -- Compiling module glbl
# 
# Top level modules:
# 	glbl
# vsim -L xilinxcorelib_ver -L unisims_ver -lib work -t 1ps adder4_adder4t_v_tf glbl 
# Loading work.adder4_adder4t_v_tf
# ** Error: (vsim-19) Failed to access library 'xilinxcorelib_ver' at "xilinxcorelib_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# Loading work.adder4
# ** Warning: (vsim-3009) [TSCALE] - Module 'adder4' does not have a `timescale directive in effect, but previous modules do.
#         Region: /adder4_adder4t_v_tf/adder
# Loading work.glbl
# .wave
# .main_pane.workspace
# .main_pane.signals.interior.cs
#                    0   0  +  0 +0 = {0, 0}
#                    5   0  +  0 +1 = {0, 1}
#                   10   1  +  1 +0 = {0, 2}
#                   15   1  +  1 +1 = {0, 3}
#                   20   2  +  2 +0 = {0, 4}
#                   25   2  +  2 +1 = {0, 5}
#                   30   3  +  3 +0 = {0, 6}
#                   35   3  +  3 +1 = {0, 7}
#                   40   4  +  4 +0 = {0, 8}
#                   45   4  +  4 +1 = {0, 9}
#                   50   5  +  5 +0 = {0,10}
#                   55   5  +  5 +1 = {0,11}
#                   60   6  +  6 +0 = {0,12}
#                   65   6  +  6 +1 = {0,13}
#                   70   7  +  7 +0 = {0,14}
#                   75   7  +  7 +1 = {0,15}
#                   80   8  +  8 +0 = {1, 0}
#                   85   8  +  8 +1 = {1, 1}
#                   90   9  +  9 +0 = {1, 2}
#                   95   9  +  9 +1 = {1, 3}
#                  100  10  + 10 +0 = {1, 4}
#                  105  10  + 10 +1 = {1, 5}
#                  110  11  + 11 +0 = {1, 6}
#                  115  11  + 11 +1 = {1, 7}
#                  120  12  + 12 +0 = {1, 8}
#                  125  12  + 12 +1 = {1, 9}
#                  130  13  + 13 +0 = {1,10}
#                  135  13  + 13 +1 = {1,11}
#                  140  14  + 14 +0 = {1,12}
#                  145  14  + 14 +1 = {1,13}
#                  150  15  + 15 +0 = {1,14}
#                  155  15  + 15 +1 = {1,15}
# ** Note: $finish    : adder4t.v(46)
#    Time: 160 ns  Iteration: 0  Instance: /adder4_adder4t_v_tf
# 1
# Break at adder4t.v line 46
# Simulation Breakpoint: 1
# Break at adder4t.v line 46
# MACRO ./adder4_adder4t_v_tf.fdo PAUSED at line 14