adder4.ldo

来自「这是个基于 Xilinx Spartan3 的加法器」· LDO 代码 · 共 13 行

# Auto generated by Project Navigator for Modelsim
vlib work

vlog  adder4.v
vlog  "D:/Xilinx/verilog/src/glbl.v"
## You need to generate your own stimuli
vsim -t 1ps +maxdelays -L xilinxcorelib_ver -L unisims_ver  adder4 glbl

view wave
add wave *
view structure
view signals