📄 adder4_adder4t_v_tf.fdo
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## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Tue Dec 27 16:52:21 中国标准时间 2005
##
vlib work
vlog adder4.v
vlog adder4t.v
vlog "D:/Xilinx/verilog/src/glbl.v"
vsim -t 1ps -L xilinxcorelib_ver -L unisims_ver -lib work adder4_adder4t_v_tf glbl
do adder4_adder4t_v_tf.udo
view wave
add wave *
view structure
view signals
run 1000ns
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