english.txt

Image_Filter_An_Image_halftone is performed over data loaded into the on board RAM and presented on

5TH YEAR OF TELECOMMUNICATION ENGINEERING
UNIVERSITY OF SEVILLE.
DIGITAL MICROELECTRONIC LABORATORY.
PROJECT: DIGITAL IMAGE PROCESSING. HALFTONNING AND BINARIZATION.
SUMMARY OF THE DESIGN.- 

The starting point is a grey scale image, and a communication VHDL module
provided by the teachers of the lab to interpretate the protocol of the 
parallel port. The aim is always a binary image, but showing up
the differences between binarization technique, which processes pixel by
pixel, and halftonning technique, which processes mask by mask. So the 
last one takes into account the medium brightness level in the mask, and 
because of that, it provides less distortion result respect to the original
image.
The complete design has considerated two separated tasks or blocks. The first
one, "Topcom", communicates with the user to receive the original image for
the RAM in the board, then it orders the required processing, and finally 
it provides the right image solicited by the user. The second block, "Toptrata",
executes the whole image processing, and besides it shows the type on the 7-segment
led.

	Component TOPCOM.- 
This block is in charge with the external communications, between the XS40 board and the PC.
At a first stage, the "sppinterf" block receives one by one the original pixels, and the one
and only finite state machine in TOPCOM sends those data to their rigth positions in the RAM.
Afterwards, the user applies for one type of processing, and this component sets up the process
in TOPTRATA. Finally, an order to read one half of the RAM is waited, then provides this image
through the parallel port, and the state machine returns to the initial state for a new image loading.
Despite being synchronous with the clock, the write and read enables are high logic active and may
long more than one cycle, and so an special analysis is needed. Summing up, there are three temporal
steps: image reading (from the PC, that is, image writing in the RAM), processing (by TOPTRATA), and
image writing (to the PC, that is, image reading from the RAM).

	Component TOPTRATA.-
In the repose state, a "0" is shown on the 7-segment led. When it receives the size 
of the processing mask from "TOPCOM", the 7-segment led indicates the type. At the 
same time, the two main finite state machines starts to communicate with each other,
one reading the original data and operating on then, and the other one writing the 
processed image in the second half of the RAM. Both of them control their respective
addresses to access to the right part of the RAM. To manage this, the design contains
two counters, one giving the address of the first pixel at every row, and the other
one reading over the columns. Those addresses are added to obtain the right position
of the first pixel in the current mask; beginning with it, the other pixels of the mask
are selected in two multiplexors, one for each part of the RAM. When the process is
ended, the machines return to the initial state and wait for a new order.