top.tan.rpt

基于FPGA液晶控制器设计与实现

+-----------------------------------------------------------------------------------------------+-----------+----------------------------------+----------------------------------+--------------------------------------------+-----------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+
; Type                                                                                          ; Slack     ; Required Time                    ; Actual Time                      ; From                                       ; To                                      ; From Clock                                                                     ; To Clock                                                                       ; Failed Paths ;
+-----------------------------------------------------------------------------------------------+-----------+----------------------------------+----------------------------------+--------------------------------------------+-----------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+
; Worst-case tsu                                                                                ; N/A       ; None                             ; 5.689 ns                         ; nRESET                                     ; reset:p_reset_comb|resrtTemp1           ; --                                                                             ; CLK                                                                            ; 0            ;
; Worst-case tco                                                                                ; N/A       ; None                             ; 16.165 ns                        ; lcd:p_lcd_comb|showData[1]                 ; lcd_Data[0]                             ; CLK                                                                            ; --                                                                             ; 0            ;
; Worst-case th                                                                                 ; N/A       ; None                             ; -5.637 ns                        ; nRESET                                     ; reset:p_reset_comb|resrtTemp1           ; --                                                                             ; CLK                                                                            ; 0            ;
; Clock Setup: 'CLK'                                                                            ; 14.321 ns ; 50.00 MHz ( period = 20.000 ns ) ; 176.09 MHz ( period = 5.679 ns ) ; reset:p_reset_comb|counter[4]              ; reset:p_reset_comb|counter[19]          ; CLK                                                                            ; CLK                                                                            ; 0            ;
; Clock Setup: 'clockGroups:p_clockGroups_comb|systemPLL:pll_pro|altpll:altpll_component|_clk0' ; 14.564 ns ; 25.00 MHz ( period = 40.000 ns ) ; 91.98 MHz ( period = 10.872 ns ) ; clockGroups:p_clockGroups_comb|tempPulse1K ; lcd:p_lcd_comb|lcdAddr[2]               ; clockGroups:p_clockGroups_comb|systemPLL:pll_pro|altpll:altpll_component|_clk0 ; clockGroups:p_clockGroups_comb|systemPLL:pll_pro|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'clockGroups:p_clockGroups_comb|systemPLL:pll_pro|altpll:altpll_component|_clk0'  ; 0.873 ns  ; 25.00 MHz ( period = 40.000 ns ) ; N/A                              ; lcd_test:p_lcd_test_comb|tempChangData1    ; lcd_test:p_lcd_test_comb|tempChangData2 ; clockGroups:p_clockGroups_comb|systemPLL:pll_pro|altpll:altpll_component|_clk0 ; clockGroups:p_clockGroups_comb|systemPLL:pll_pro|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'CLK'                                                                             ; 1.878 ns  ; 50.00 MHz ( period = 20.000 ns ) ; N/A                              ; reset:p_reset_comb|counter[0]              ; reset:p_reset_comb|counter[0]           ; CLK                                                                            ; CLK                                                                            ; 0            ;
; Total number of failed paths                                                                  ;           ;                                  ;                                  ;                                            ;                                         ;                                                                                ;                                                                                ; 0            ;
+-----------------------------------------------------------------------------------------------+-----------+----------------------------------+----------------------------------+--------------------------------------------+-----------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C12Q240C8       ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; On                 ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                                                              ;
+--------------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name                                                                ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+--------------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+