top.tan.summary

基于FPGA液晶控制器设计与实现

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.689 ns
From           : nRESET
To             : reset:p_reset_comb|resrtTemp1
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 16.165 ns
From           : lcd:p_lcd_comb|showData[1]
To             : lcd_Data[0]
From Clock     : CLK
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -5.637 ns
From           : nRESET
To             : reset:p_reset_comb|resrtTemp1
From Clock     : --
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'CLK'
Slack          : 14.321 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : 176.09 MHz ( period = 5.679 ns )
From           : reset:p_reset_comb|counter[4]
To             : reset:p_reset_comb|counter[19]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Clock Setup: 'clockGroups:p_clockGroups_comb|systemPLL:pll_pro|altpll:altpll_component|_clk0'
Slack          : 14.564 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : 91.98 MHz ( period = 10.872 ns )
From           : clockGroups:p_clockGroups_comb|tempPulse1K
To             : lcd:p_lcd_comb|lcdAddr[2]
From Clock     : clockGroups:p_clockGroups_comb|systemPLL:pll_pro|altpll:altpll_component|_clk0
To Clock       : clockGroups:p_clockGroups_comb|systemPLL:pll_pro|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'clockGroups:p_clockGroups_comb|systemPLL:pll_pro|altpll:altpll_component|_clk0'
Slack          : 0.873 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : N/A
From           : lcd_test:p_lcd_test_comb|tempChangData1
To             : lcd_test:p_lcd_test_comb|tempChangData2
From Clock     : clockGroups:p_clockGroups_comb|systemPLL:pll_pro|altpll:altpll_component|_clk0
To Clock       : clockGroups:p_clockGroups_comb|systemPLL:pll_pro|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'CLK'
Slack          : 1.878 ns
Required Time  : 50.00 MHz ( period = 20.000 ns )
Actual Time    : N/A
From           : reset:p_reset_comb|counter[0]
To             : reset:p_reset_comb|counter[0]
From Clock     : CLK
To Clock       : CLK
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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