lcd_test.vhd

基于FPGA液晶控制器设计与实现

-- -----------------------------------------------------------------------------
--
-- 文件名 : lcd_test.vhd
--
-- 功能   : 生成数据发送给 lcd 模块,用以测试 lcd 模块.
--
-- 端口   : CLK_Z       : in     25MHz , 50% 占空比的时钟信号.
--          pulse1K     : in    1KHz 的 脉冲信号, 占空比很小.
--          RESET       : in    大于671.08864ms的 复位 信号.
--
--          enable      : out   写显示寄存器的使能信号.
--          wren        : out   写显示寄存器的使能信号.
--          writeAddr   : out   写显示寄存器的地址.
--          writeData   : out   写显示寄存器的数据.
--
-- 笔记   :
--
-- Total logic elements:  39/12,060 ( <1%)
-- -----------------------------------------------------------------------------
-- 建立日期 : 2007/4/15
-- -----------------------------------------------------------------------------
-- 修改日期 :
-- 修改内容 :
-- -----------------------------------------------------------------------------

library ieee;
	use ieee.std_logic_1164.all;
	use ieee.std_logic_unsigned.all;

entity lcd_test is
	port (
		CLK_Z            : in  std_logic;
		pulse1K          : in  std_logic;

		RESET            : in  std_logic;

		enable           : out std_logic;
		wren             : out std_logic;
		writeAddr        : out std_logic_vector(2 downto 0);
		writeData        : out std_logic_vector(15 downto 0)
	);
end lcd_test;

architecture RTL of lcd_test is

	signal coun1Hz,    tempCoun1Hz                     : std_logic_vector(8 downto 0);
	signal pulse1Hz,  tempPulse1Hz                     : std_logic;

	signal changData, tempChangData1, tempChangData2   : std_logic;

	signal lcdAddr, tempLcdAddr          : std_logic_vector(2 downto 0);
	signal lcdData, tempLcdData          : std_logic_vector(15 downto 0);
begin

	enable       <= pulse1Hz;
	wren         <= pulse1Hz;
	writeAddr    <= lcdAddr;
	writeData    <= lcdData;

	--------- 输出 到 LCD模块 的 地址数据 和 显示数据 ----------------------------
	tempLcdAddr <= lcdAddr + '1';
	tempLcdData <= lcdData + '1';
	lcdData_pro: process (RESET, CLK_Z, changData, tempLcdAddr, tempLcdData)
	begin
		if (RESET = '1') then
			lcdAddr   <=  "000";
			lcdData   <=  "0000000000000000";
		elsif (CLK_Z'event and CLK_Z = '1' and changData = '1') then --上升沿
			lcdAddr      <=  tempLcdAddr;
			lcdData      <=  tempLcdData;
		end if;
	end process;

	------------ 在 1Hz脉冲的上升沿 产生一个改变输出数据的使能信号 ----------------------
	changData <= tempChangData1 and (not tempChangData2);
	enable_pro : process(CLK_Z, coun1Hz, tempChangData1)
	begin
		if (CLK_Z'event and CLK_Z = '0')then  --下降沿
			tempChangData1      <=  pulse1Hz;
			tempChangData2      <=  tempChangData1;
		end if;
	end process;

	----------------- 产生 1Hz 的脉冲 --------------------------------------------
	pulse1Hz <= tempPulse1Hz;

	tempCoun1Hz <= coun1Hz + '1';
	pulse1Hz_pro : process(CLK_Z, pulse1K, tempCoun1Hz)
	begin
		if (CLK_Z'event and CLK_Z = '1' and pulse1K = '1') then  --上升沿
			if (tempCoun1Hz = "110010000") then
				coun1Hz      <= "000000000";
				tempPulse1Hz <= '1';
			else
				coun1Hz      <= tempCoun1Hz;
				tempPulse1Hz <= '0';
			end if;
		end if;
	end process;

end RTL;