muxh_tp.v

Verilog 编写的fir滤波器

module muxh_tp;    //h(i)输出的mux的测试模块
reg reset,clk2;
reg [63:0] hin;  
wire [7:0] hout;
reg [3:0] n,nextn;      
parameter DELY=100;
muxh mymuxh(reset,clk2,n,hin,hout);  //h(i)输出的mux模块
always@(n or reset)        //使n满足控制信号的条件从0到9变化
  begin
   if(!reset)  nextn=0;
   else
     begin
        case(n)
           0:   nextn=1;
           1:  nextn=2;
           2:   nextn=3;
           3:    nextn=4;
           4:    nextn=5; 
           5:   nextn=6; 
           6:   nextn=7; 
           7:   nextn=8; 
           8:   nextn=9; 
           9:   nextn=0; 
           default:   nextn=0; 
       endcase
     end
   end
always #(DELY) n=nextn; 
always #(DELY/2)clk2=~clk2;
initial
begin n=0;reset=1;hin=0;clk2=1;
#DELY reset=0;
#DELY reset=1;   
#DELY hin=64'b0100110011110011111111110000010111111100000000100000000000000000;      //输入滤波器的系数
#(DELY*50) $finish;
end
initial $monitor($time,,,"reset=%d clk2=%d n=%d hin=%d hout=%d",reset,clk2,n,hin,hout);
endmodule