mux_tp.v

来自「Verilog 编写的fir滤波器」· Verilog 代码 · 共 38 行

module mux_tp;        //x输入选择模块
reg reset,clk2;    //输入清零和时钟信号
reg [3:0] n,nextn;  //输入控制信号n
reg [127:0] xin;   //输入x(0)~x(15)
wire [7:0] xout1,xout2;   //输出x(i)和x(N-i-1)
parameter DELY=100;
mux mymux(reset,clk2,n,xin,xout1,xout2);//调用选择模块程序
always@(n or reset)   //使n满足控制信号的条件从0到9变化
  begin
   if(!reset)  nextn=0;
   else
     begin
        case(n)
           0:   nextn=1;
           1:  nextn=2;
           2:   nextn=3;
           3:    nextn=4;
           4:    nextn=5; 
           5:   nextn=6; 
           6:   nextn=7; 
           7:   nextn=8; 
           8:   nextn=9; 
           9:   nextn=0; 
           default:   nextn=0; 
       endcase
     end
   end
always #(DELY) n=nextn; 
always #(DELY/2)clk2=~clk2;
initial
begin n=0;reset=1;xin=0;clk2=1;
#DELY reset=0;
#DELY reset=1;   
#DELY xin[31:0]=54564354;xin[63:32]=85414741;xin[95:64]=78561234;xin[127:96]=45656885;  //分四次输入x(0)~x(15)寄存器
#(DELY*50) $finish;
end
initial $monitor($time,,," reset=%d clk2=%d n=%d xin=%d xout1=%d xout2=%d",reset,clk2,n,xin,xout1,xout2);
endmodule