shifter_tp.v

Verilog 编写的fir滤波器

module shifter_tp;  //移位寄存器测试模块
reg clk1,reset;   //输入时钟信号1和清零信号
reg [7:0] xin;    //输入x
wire [127:0] xout;  //定义输出寄存器型数组
parameter DELY=100;
shifter myshifter(clk1,reset,xin,xout);   //调用移位寄存器模块
always #(DELY/2) clk1=~clk1;
initial
begin clk1=0;reset=1;xin=0;    
#DELY reset=0;
#DELY reset=1;     
#DELY xin=34;      //没隔clk1输入一个x
#DELY xin=85;
#DELY xin=75;
#DELY xin=95;
#DELY xin=10;
#DELY xin=04;
#DELY xin=65;
#DELY xin=89;
#DELY xin=41;
#DELY xin=98;
#DELY xin=37;
#DELY xin=93;
#DELY xin=123;
#DELY xin=58;
#DELY xin=22;
#DELY xin=30;
#DELY xin=55;
#DELY xin=74;
#DELY xin=63;
#DELY xin=34;
#(DELY*50) $finish;
end
initial $monitor($time,,,"clk1=%d reset=%d xin=%d xout=%d",clk1,reset,xin,xout);
endmodule